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Searched refs:REG_DVI_DTOP1_29_L (Results 1 – 25 of 28) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_mux.c236 W2BYTEMSK( REG_DVI_DTOP1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
265 … W2BYTEMSK( REG_DVI_DTOP1_29_L, 0xE300, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
268 … W2BYTEMSK( REG_DVI_DTOP1_29_L, 0, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
308 W2BYTEMSK( REG_DVI_DTOP1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
343 W2BYTEMSK( REG_DVI_DTOP1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c1132 … W2BYTEMSK( REG_DVI_DTOP1_29_L, 0, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_HDMI_init()
1156 … W2BYTEMSK( REG_DVI_DTOP1_29_L, 0xE300, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_HDMI_init()
2698 W2BYTEMSK( REG_DVI_DTOP1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_mux.c236 W2BYTEMSK( REG_DVI_DTOP1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
265 … W2BYTEMSK( REG_DVI_DTOP1_29_L, 0xE300, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
268 … W2BYTEMSK( REG_DVI_DTOP1_29_L, 0, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
308 W2BYTEMSK( REG_DVI_DTOP1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
343 W2BYTEMSK( REG_DVI_DTOP1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c1132 … W2BYTEMSK( REG_DVI_DTOP1_29_L, 0, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_HDMI_init()
1156 … W2BYTEMSK( REG_DVI_DTOP1_29_L, 0xE300, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_HDMI_init()
2698 W2BYTEMSK( REG_DVI_DTOP1_29_L, 0, BIT(15)); // [15]: turn off slowly updated in Hal_DVI_ForceAllPortsEnterPS()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_mux.c245 … W2BYTEMSK( REG_DVI_DTOP1_29_L, 0xE300, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_mux.c245 … W2BYTEMSK( REG_DVI_DTOP1_29_L, 0xE300, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_mux.c245 … W2BYTEMSK( REG_DVI_DTOP1_29_L, 0xE300, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_mux.c245 … W2BYTEMSK( REG_DVI_DTOP1_29_L, 0xE300, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_mux.c245 … W2BYTEMSK( REG_DVI_DTOP1_29_L, 0xE300, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_mux.c245 … W2BYTEMSK( REG_DVI_DTOP1_29_L, 0xE300, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_mux.c245 … W2BYTEMSK( REG_DVI_DTOP1_29_L, 0xE300, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_mux.c245 … W2BYTEMSK( REG_DVI_DTOP1_29_L, 0xE300, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_mux.c245 … W2BYTEMSK( REG_DVI_DTOP1_29_L, 0xE300, HBMASK); // [15]:update Bch slowly; [14:8]: 0x63(100 lines) in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_hdmi.h265 #define REG_DVI_DTOP1_29_L (REG_DVI_DTOP1_BASE + 0x52) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_hdmi.h265 #define REG_DVI_DTOP1_29_L (REG_DVI_DTOP1_BASE + 0x52) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h261 #define REG_DVI_DTOP1_29_L (REG_DVI_DTOP1_BASE + 0x52) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h261 #define REG_DVI_DTOP1_29_L (REG_DVI_DTOP1_BASE + 0x52) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h261 #define REG_DVI_DTOP1_29_L (REG_DVI_DTOP1_BASE + 0x52) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h261 #define REG_DVI_DTOP1_29_L (REG_DVI_DTOP1_BASE + 0x52) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h261 #define REG_DVI_DTOP1_29_L (REG_DVI_DTOP1_BASE + 0x52) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h261 #define REG_DVI_DTOP1_29_L (REG_DVI_DTOP1_BASE + 0x52) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h261 #define REG_DVI_DTOP1_29_L (REG_DVI_DTOP1_BASE + 0x52) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h261 #define REG_DVI_DTOP1_29_L (REG_DVI_DTOP1_BASE + 0x52) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h261 #define REG_DVI_DTOP1_29_L (REG_DVI_DTOP1_BASE + 0x52) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h261 #define REG_DVI_DTOP1_29_L (REG_DVI_DTOP1_BASE + 0x52) macro

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