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Searched refs:REG_DVI_ATOP_6A_L (Results 1 – 25 of 50) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_mux.c257 W2BYTEMSK(REG_DVI_ATOP_6A_L, 0, BMASK(1:0)); // switch display port to port 0 in Hal_SC_mux_set_dvi_mux()
293 W2BYTEMSK(REG_DVI_ATOP_6A_L, BIT(0), BMASK(1:0)); // switch display port to port 0 in Hal_SC_mux_set_dvi_mux()
328 W2BYTEMSK(REG_DVI_ATOP_6A_L, BIT(1), BMASK(1:0)); // switch display port to port 0 in Hal_SC_mux_set_dvi_mux()
363 W2BYTEMSK(REG_DVI_ATOP_6A_L, BMASK(1:0), BMASK(1:0)); // switch display port to port 0 in Hal_SC_mux_set_dvi_mux()
402 W2BYTEMSK(REG_DVI_ATOP_6A_L, 0, BMASK(1:0)); // switch display port to port 0 in Hal_SC_mux_set_dvi_mux()
435 W2BYTEMSK(REG_DVI_ATOP_6A_L, BIT(0), BMASK(1:0)); // switch display port to port 1 in Hal_SC_mux_set_dvi_mux()
468 W2BYTEMSK(REG_DVI_ATOP_6A_L, BIT(1), BMASK(1:0)); // switch display port to port 3 in Hal_SC_mux_set_dvi_mux()
501 … W2BYTEMSK(REG_DVI_ATOP_6A_L, BMASK(1:0), BMASK(1:0)); // switch display port to port 2 in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c2566 W2BYTEMSK(REG_DVI_ATOP_6A_L, 0, BMASK(1:0)); in Hal_DVI_SwitchSrc()
2570 W2BYTEMSK(REG_DVI_ATOP_6A_L, 1, BMASK(1:0)); in Hal_DVI_SwitchSrc()
2574 W2BYTEMSK(REG_DVI_ATOP_6A_L, 2, BMASK(1:0)); in Hal_DVI_SwitchSrc()
2578 W2BYTEMSK(REG_DVI_ATOP_6A_L, 3, BMASK(1:0)); in Hal_DVI_SwitchSrc()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_mux.c257 W2BYTEMSK(REG_DVI_ATOP_6A_L, 0, BMASK(1:0)); // switch display port to port 0 in Hal_SC_mux_set_dvi_mux()
293 W2BYTEMSK(REG_DVI_ATOP_6A_L, BIT(0), BMASK(1:0)); // switch display port to port 0 in Hal_SC_mux_set_dvi_mux()
328 W2BYTEMSK(REG_DVI_ATOP_6A_L, BIT(1), BMASK(1:0)); // switch display port to port 0 in Hal_SC_mux_set_dvi_mux()
363 W2BYTEMSK(REG_DVI_ATOP_6A_L, BMASK(1:0), BMASK(1:0)); // switch display port to port 0 in Hal_SC_mux_set_dvi_mux()
402 W2BYTEMSK(REG_DVI_ATOP_6A_L, 0, BMASK(1:0)); // switch display port to port 0 in Hal_SC_mux_set_dvi_mux()
435 W2BYTEMSK(REG_DVI_ATOP_6A_L, BIT(0), BMASK(1:0)); // switch display port to port 1 in Hal_SC_mux_set_dvi_mux()
468 W2BYTEMSK(REG_DVI_ATOP_6A_L, BIT(1), BMASK(1:0)); // switch display port to port 3 in Hal_SC_mux_set_dvi_mux()
501 … W2BYTEMSK(REG_DVI_ATOP_6A_L, BMASK(1:0), BMASK(1:0)); // switch display port to port 2 in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c2566 W2BYTEMSK(REG_DVI_ATOP_6A_L, 0, BMASK(1:0)); in Hal_DVI_SwitchSrc()
2570 W2BYTEMSK(REG_DVI_ATOP_6A_L, 1, BMASK(1:0)); in Hal_DVI_SwitchSrc()
2574 W2BYTEMSK(REG_DVI_ATOP_6A_L, 2, BMASK(1:0)); in Hal_DVI_SwitchSrc()
2578 W2BYTEMSK(REG_DVI_ATOP_6A_L, 3, BMASK(1:0)); in Hal_DVI_SwitchSrc()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_hdmi.c2745 temp = (R2BYTE(REG_DVI_ATOP_6A_L) & 0x0300)>>8; in Hal_DVI_HF_adjust()
3038 W2BYTEMSK(REG_DVI_ATOP_6A_L, 0, BMASK(1:0)); in Hal_DVI_SwitchSrc()
3042 W2BYTEMSK(REG_DVI_ATOP_6A_L, 0, BMASK(1:0)); in Hal_DVI_SwitchSrc()
3046 W2BYTEMSK(REG_DVI_ATOP_6A_L, 0, BMASK(1:0)); in Hal_DVI_SwitchSrc()
3050 W2BYTEMSK(REG_DVI_ATOP_6A_L, 0, BMASK(1:0)); in Hal_DVI_SwitchSrc()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_hdmi.c3482 temp = (R2BYTE(REG_DVI_ATOP_6A_L) & 0x0300)>>8; in Hal_DVI_HF_adjust()
3775 W2BYTEMSK(REG_DVI_ATOP_6A_L, 0, BMASK(1:0)); in Hal_DVI_SwitchSrc()
3779 W2BYTEMSK(REG_DVI_ATOP_6A_L, 0, BMASK(1:0)); in Hal_DVI_SwitchSrc()
3783 W2BYTEMSK(REG_DVI_ATOP_6A_L, 0, BMASK(1:0)); in Hal_DVI_SwitchSrc()
3787 W2BYTEMSK(REG_DVI_ATOP_6A_L, 0, BMASK(1:0)); in Hal_DVI_SwitchSrc()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_dvi_atop.h314 #define REG_DVI_ATOP_6A_L (REG_DVI_ATOP_BASE + 0xD4) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_dvi_atop.h314 #define REG_DVI_ATOP_6A_L (REG_DVI_ATOP_BASE + 0xD4) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_dvi_atop.h314 #define REG_DVI_ATOP_6A_L (REG_DVI_ATOP_BASE + 0xD4) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_dvi_atop.h314 #define REG_DVI_ATOP_6A_L (REG_DVI_ATOP_BASE + 0xD4) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_dvi_atop.h314 #define REG_DVI_ATOP_6A_L (REG_DVI_ATOP_BASE + 0xD4) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_dvi_atop.h314 #define REG_DVI_ATOP_6A_L (REG_DVI_ATOP_BASE + 0xD4) macro
H A Dhwreg_hdmi.h745 #define REG_DVI_ATOP_6A_L (REG_DVI_ATOP_BASE + 0xD4) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_dvi_atop.h314 #define REG_DVI_ATOP_6A_L (REG_DVI_ATOP_BASE + 0xD4) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_dvi_atop.h314 #define REG_DVI_ATOP_6A_L (REG_DVI_ATOP_BASE + 0xD4) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_dvi_atop.h314 #define REG_DVI_ATOP_6A_L (REG_DVI_ATOP_BASE + 0xD4) macro
H A Dhwreg_hdmi.h745 #define REG_DVI_ATOP_6A_L (REG_DVI_ATOP_BASE + 0xD4) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_dvi_atop.h314 #define REG_DVI_ATOP_6A_L (REG_DVI_ATOP_BASE + 0xD4) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_dvi_atop.h314 #define REG_DVI_ATOP_6A_L (REG_DVI_ATOP_BASE + 0xD4) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_dvi_atop.h314 #define REG_DVI_ATOP_6A_L (REG_DVI_ATOP_BASE + 0xD4) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_dvi_atop.h314 #define REG_DVI_ATOP_6A_L (REG_DVI_ATOP_BASE + 0xD4) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_dvi_atop.h314 #define REG_DVI_ATOP_6A_L (REG_DVI_ATOP_BASE + 0xD4) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_dvi_atop.h314 #define REG_DVI_ATOP_6A_L (REG_DVI_ATOP_BASE + 0xD4) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/mhl/internal/
H A DhalMHL.c1255 W2BYTEMSK(REG_DVI_ATOP_6A_L, (ucClockSelect << 2), BMASK(3:2)); // [3:2]: HDCP clock select in _mhal_mhl_CbusAndClockSelect()
1377 return (R2BYTE(REG_DVI_ATOP_6A_L) &BMASK(1:0)); in mhal_mhl_GetInputPort()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/mhl/internal/
H A DhalMHL.c1255 W2BYTEMSK(REG_DVI_ATOP_6A_L, (ucClockSelect << 2), BMASK(3:2)); // [3:2]: HDCP clock select in _mhal_mhl_CbusAndClockSelect()
1377 return (R2BYTE(REG_DVI_ATOP_6A_L) &BMASK(1:0)); in mhal_mhl_GetInputPort()

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