| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/ |
| H A D | mhal_mux.c | 382 W2BYTEMSK(REG_DVI_ATOP_69_L, 0xFFDF, 0xFFDF); // disable DVI3 PLL power in Hal_SC_mux_set_dvi_mux()
395 W2BYTE(REG_DVI_ATOP_69_L, 0xFFFF); // disable DVI3 PLL power in Hal_SC_mux_set_dvi_mux()
415 W2BYTEMSK(REG_DVI_ATOP_69_L, 0xFFDF, 0xFFDF); // disable DVI3 PLL power in Hal_SC_mux_set_dvi_mux()
428 W2BYTE(REG_DVI_ATOP_69_L, 0xFFFF); // disable DVI3 PLL power in Hal_SC_mux_set_dvi_mux()
448 W2BYTEMSK(REG_DVI_ATOP_69_L, 0xFFDF, 0xFFDF); // disable DVI3 PLL power in Hal_SC_mux_set_dvi_mux()
461 W2BYTE(REG_DVI_ATOP_69_L, 0xFFFF); // disable DVI3 PLL power in Hal_SC_mux_set_dvi_mux()
481 W2BYTEMSK(REG_DVI_ATOP_69_L, 0, 0xFFFF); // enable DVI3 PLL power in Hal_SC_mux_set_dvi_mux()
494 W2BYTE(REG_DVI_ATOP_69_L, 0); // enable DVI3 PLL power in Hal_SC_mux_set_dvi_mux()
514 W2BYTEMSK(REG_DVI_ATOP_69_L, 0xFFDF, 0xFFDF); // disable DVI3 PLL power in Hal_SC_mux_set_dvi_mux()
527 W2BYTE(REG_DVI_ATOP_69_L, 0xFFFF); // disable DVI3 PLL power in Hal_SC_mux_set_dvi_mux()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/ |
| H A D | mhal_mux.c | 382 W2BYTEMSK(REG_DVI_ATOP_69_L, 0xFFDF, 0xFFDF); // disable DVI3 PLL power in Hal_SC_mux_set_dvi_mux()
395 W2BYTE(REG_DVI_ATOP_69_L, 0xFFFF); // disable DVI3 PLL power in Hal_SC_mux_set_dvi_mux()
415 W2BYTEMSK(REG_DVI_ATOP_69_L, 0xFFDF, 0xFFDF); // disable DVI3 PLL power in Hal_SC_mux_set_dvi_mux()
428 W2BYTE(REG_DVI_ATOP_69_L, 0xFFFF); // disable DVI3 PLL power in Hal_SC_mux_set_dvi_mux()
448 W2BYTEMSK(REG_DVI_ATOP_69_L, 0xFFDF, 0xFFDF); // disable DVI3 PLL power in Hal_SC_mux_set_dvi_mux()
461 W2BYTE(REG_DVI_ATOP_69_L, 0xFFFF); // disable DVI3 PLL power in Hal_SC_mux_set_dvi_mux()
481 W2BYTEMSK(REG_DVI_ATOP_69_L, 0, 0xFFFF); // enable DVI3 PLL power in Hal_SC_mux_set_dvi_mux()
494 W2BYTE(REG_DVI_ATOP_69_L, 0); // enable DVI3 PLL power in Hal_SC_mux_set_dvi_mux()
514 W2BYTEMSK(REG_DVI_ATOP_69_L, 0xFFDF, 0xFFDF); // disable DVI3 PLL power in Hal_SC_mux_set_dvi_mux()
527 W2BYTE(REG_DVI_ATOP_69_L, 0xFFFF); // disable DVI3 PLL power in Hal_SC_mux_set_dvi_mux()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_dvi_atop.h | 312 #define REG_DVI_ATOP_69_L (REG_DVI_ATOP_BASE + 0xD2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/ |
| H A D | hwreg_dvi_atop.h | 312 #define REG_DVI_ATOP_69_L (REG_DVI_ATOP_BASE + 0xD2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_dvi_atop.h | 312 #define REG_DVI_ATOP_69_L (REG_DVI_ATOP_BASE + 0xD2) macro
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| H A D | hwreg_hdmi.h | 737 #define REG_DVI_ATOP_69_L (REG_DVI_ATOP_BASE + 0xD2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_dvi_atop.h | 312 #define REG_DVI_ATOP_69_L (REG_DVI_ATOP_BASE + 0xD2) macro
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| H A D | hwreg_hdmi.h | 737 #define REG_DVI_ATOP_69_L (REG_DVI_ATOP_BASE + 0xD2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_dvi_atop.h | 312 #define REG_DVI_ATOP_69_L (REG_DVI_ATOP_BASE + 0xD2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/ |
| H A D | hwreg_dvi_atop.h | 312 #define REG_DVI_ATOP_69_L (REG_DVI_ATOP_BASE + 0xD2) macro
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| H A D | hwreg_hdmi.h | 743 #define REG_DVI_ATOP_69_L (REG_DVI_ATOP_BASE + 0xD2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_dvi_atop.h | 312 #define REG_DVI_ATOP_69_L (REG_DVI_ATOP_BASE + 0xD2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_dvi_atop.h | 312 #define REG_DVI_ATOP_69_L (REG_DVI_ATOP_BASE + 0xD2) macro
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| H A D | hwreg_hdmi.h | 737 #define REG_DVI_ATOP_69_L (REG_DVI_ATOP_BASE + 0xD2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/ |
| H A D | hwreg_dvi_atop.h | 312 #define REG_DVI_ATOP_69_L (REG_DVI_ATOP_BASE + 0xD2) macro
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| H A D | hwreg_hdmi.h | 743 #define REG_DVI_ATOP_69_L (REG_DVI_ATOP_BASE + 0xD2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_dvi_atop.h | 312 #define REG_DVI_ATOP_69_L (REG_DVI_ATOP_BASE + 0xD2) macro
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| H A D | hwreg_hdmi.h | 737 #define REG_DVI_ATOP_69_L (REG_DVI_ATOP_BASE + 0xD2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_dvi_atop.h | 312 #define REG_DVI_ATOP_69_L (REG_DVI_ATOP_BASE + 0xD2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_dvi_atop.h | 312 #define REG_DVI_ATOP_69_L (REG_DVI_ATOP_BASE + 0xD2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_dvi_atop.h | 312 #define REG_DVI_ATOP_69_L (REG_DVI_ATOP_BASE + 0xD2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_dvi_atop.h | 312 #define REG_DVI_ATOP_69_L (REG_DVI_ATOP_BASE + 0xD2) macro
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| H A D | hwreg_hdmi.h | 737 #define REG_DVI_ATOP_69_L (REG_DVI_ATOP_BASE + 0xD2) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_dvi_atop.h | 312 #define REG_DVI_ATOP_69_L (REG_DVI_ATOP_BASE + 0xD2) macro
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| H A D | hwreg_hdmi.h | 737 #define REG_DVI_ATOP_69_L (REG_DVI_ATOP_BASE + 0xD2) macro
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