| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/ |
| H A D | mhal_mux.c | 377 W2BYTEMSK(REG_DVI_ATOP_03_L, 0x7FFE, 0x7FFE); // disable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
390 W2BYTEMSK(REG_DVI_ATOP_03_L, 0xFFFE, 0xFFFE); // disable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
410 W2BYTEMSK(REG_DVI_ATOP_03_L, 0x7FFE, 0x7FFE); // disable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
423 W2BYTEMSK(REG_DVI_ATOP_03_L, 0xFFFE, 0xFFFE); // disable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
443 W2BYTEMSK(REG_DVI_ATOP_03_L, 0x7FFE, 0x7FFE); // disable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
456 W2BYTEMSK(REG_DVI_ATOP_03_L, 0xFFFE, 0xFFFE); // disable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
476 W2BYTEMSK(REG_DVI_ATOP_03_L, 0, 0xFFFF); // enable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
489 W2BYTE(REG_DVI_ATOP_03_L, 0); // enable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
509 W2BYTEMSK(REG_DVI_ATOP_03_L, 0x7FFE, 0x7FFE); // enable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
522 W2BYTEMSK(REG_DVI_ATOP_03_L, 0xFFFE, 0xFFFE); // enable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/ |
| H A D | mhal_mux.c | 377 W2BYTEMSK(REG_DVI_ATOP_03_L, 0x7FFE, 0x7FFE); // disable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
390 W2BYTEMSK(REG_DVI_ATOP_03_L, 0xFFFE, 0xFFFE); // disable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
410 W2BYTEMSK(REG_DVI_ATOP_03_L, 0x7FFE, 0x7FFE); // disable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
423 W2BYTEMSK(REG_DVI_ATOP_03_L, 0xFFFE, 0xFFFE); // disable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
443 W2BYTEMSK(REG_DVI_ATOP_03_L, 0x7FFE, 0x7FFE); // disable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
456 W2BYTEMSK(REG_DVI_ATOP_03_L, 0xFFFE, 0xFFFE); // disable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
476 W2BYTEMSK(REG_DVI_ATOP_03_L, 0, 0xFFFF); // enable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
489 W2BYTE(REG_DVI_ATOP_03_L, 0); // enable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
509 W2BYTEMSK(REG_DVI_ATOP_03_L, 0x7FFE, 0x7FFE); // enable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
522 W2BYTEMSK(REG_DVI_ATOP_03_L, 0xFFFE, 0xFFFE); // enable DVI0 clock power in Hal_SC_mux_set_dvi_mux()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_dvi_atop.h | 108 #define REG_DVI_ATOP_03_L (REG_DVI_ATOP_BASE + 0x06) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/ |
| H A D | hwreg_dvi_atop.h | 108 #define REG_DVI_ATOP_03_L (REG_DVI_ATOP_BASE + 0x06) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_dvi_atop.h | 108 #define REG_DVI_ATOP_03_L (REG_DVI_ATOP_BASE + 0x06) macro
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| H A D | hwreg_hdmi.h | 533 #define REG_DVI_ATOP_03_L (REG_DVI_ATOP_BASE + 0x06) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_dvi_atop.h | 108 #define REG_DVI_ATOP_03_L (REG_DVI_ATOP_BASE + 0x06) macro
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| H A D | hwreg_hdmi.h | 533 #define REG_DVI_ATOP_03_L (REG_DVI_ATOP_BASE + 0x06) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_dvi_atop.h | 108 #define REG_DVI_ATOP_03_L (REG_DVI_ATOP_BASE + 0x06) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/ |
| H A D | hwreg_dvi_atop.h | 108 #define REG_DVI_ATOP_03_L (REG_DVI_ATOP_BASE + 0x06) macro
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| H A D | hwreg_hdmi.h | 539 #define REG_DVI_ATOP_03_L (REG_DVI_ATOP_BASE + 0x06) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_dvi_atop.h | 108 #define REG_DVI_ATOP_03_L (REG_DVI_ATOP_BASE + 0x06) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_dvi_atop.h | 108 #define REG_DVI_ATOP_03_L (REG_DVI_ATOP_BASE + 0x06) macro
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| H A D | hwreg_hdmi.h | 533 #define REG_DVI_ATOP_03_L (REG_DVI_ATOP_BASE + 0x06) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/ |
| H A D | hwreg_dvi_atop.h | 108 #define REG_DVI_ATOP_03_L (REG_DVI_ATOP_BASE + 0x06) macro
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| H A D | hwreg_hdmi.h | 539 #define REG_DVI_ATOP_03_L (REG_DVI_ATOP_BASE + 0x06) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_dvi_atop.h | 108 #define REG_DVI_ATOP_03_L (REG_DVI_ATOP_BASE + 0x06) macro
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| H A D | hwreg_hdmi.h | 533 #define REG_DVI_ATOP_03_L (REG_DVI_ATOP_BASE + 0x06) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_dvi_atop.h | 108 #define REG_DVI_ATOP_03_L (REG_DVI_ATOP_BASE + 0x06) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_dvi_atop.h | 108 #define REG_DVI_ATOP_03_L (REG_DVI_ATOP_BASE + 0x06) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_dvi_atop.h | 108 #define REG_DVI_ATOP_03_L (REG_DVI_ATOP_BASE + 0x06) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_dvi_atop.h | 108 #define REG_DVI_ATOP_03_L (REG_DVI_ATOP_BASE + 0x06) macro
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| H A D | hwreg_hdmi.h | 533 #define REG_DVI_ATOP_03_L (REG_DVI_ATOP_BASE + 0x06) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_dvi_atop.h | 108 #define REG_DVI_ATOP_03_L (REG_DVI_ATOP_BASE + 0x06) macro
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| H A D | hwreg_hdmi.h | 533 #define REG_DVI_ATOP_03_L (REG_DVI_ATOP_BASE + 0x06) macro
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