| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/ |
| H A D | mhal_mux.c | 375 W2BYTEMSK(REG_DVI_ATOP1_06_L, 0x7FFE, 0x7FFE); // disable DVI1 clock power in Hal_SC_mux_set_dvi_mux()
388 W2BYTEMSK(REG_DVI_ATOP1_06_L, 0xFFFE, 0xFFFE); // disable DVI1 clock power in Hal_SC_mux_set_dvi_mux()
408 W2BYTE(REG_DVI_ATOP1_06_L, 0); // enable DVI1 clock power in Hal_SC_mux_set_dvi_mux()
421 W2BYTE(REG_DVI_ATOP1_06_L, 0); // enable DVI1 clock power in Hal_SC_mux_set_dvi_mux()
441 W2BYTEMSK(REG_DVI_ATOP1_06_L, 0x7FFE, 0x7FFE); // disable DVI1 clock power in Hal_SC_mux_set_dvi_mux()
454 W2BYTEMSK(REG_DVI_ATOP1_06_L, 0xFFFE, 0xFFFE); // disable DVI1 clock power in Hal_SC_mux_set_dvi_mux()
474 W2BYTEMSK(REG_DVI_ATOP1_06_L, 0x7FFE, 0x7FFE); // disable DVI1 clock power in Hal_SC_mux_set_dvi_mux()
487 W2BYTEMSK(REG_DVI_ATOP1_06_L, 0xFFFE, 0xFFFE); // disable DVI1 clock power in Hal_SC_mux_set_dvi_mux()
507 W2BYTEMSK(REG_DVI_ATOP1_06_L, 0x7FFE, 0x7FFE); // disable DVI1 clock power in Hal_SC_mux_set_dvi_mux()
520 W2BYTEMSK(REG_DVI_ATOP1_06_L, 0xFFFE, 0xFFFE); // disable DVI1 clock power in Hal_SC_mux_set_dvi_mux()
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| H A D | mhal_offline.c | 395 MS_U16 u16DVIATOP_06 = R2BYTE(REG_DVI_ATOP1_06_L); in Hal_XC_GetOffLineOfDVI1()
399 W2BYTE(REG_DVI_ATOP1_06_L, 0); // enable DVI1 clock power in Hal_XC_GetOffLineOfDVI1()
416 W2BYTE(REG_DVI_ATOP1_06_L, u16DVIATOP_06); in Hal_XC_GetOffLineOfDVI1()
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| H A D | mhal_hdmi.c | 1089 W2BYTE(REG_DVI_ATOP1_06_L, 0x0000); // enable DVI1 all clock power in Hal_HDMI_init()
1149 W2BYTEMSK(REG_DVI_ATOP1_06_L, 0x0000, 0x8001); in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/ |
| H A D | mhal_mux.c | 375 W2BYTEMSK(REG_DVI_ATOP1_06_L, 0x7FFE, 0x7FFE); // disable DVI1 clock power in Hal_SC_mux_set_dvi_mux()
388 W2BYTEMSK(REG_DVI_ATOP1_06_L, 0xFFFE, 0xFFFE); // disable DVI1 clock power in Hal_SC_mux_set_dvi_mux()
408 W2BYTE(REG_DVI_ATOP1_06_L, 0); // enable DVI1 clock power in Hal_SC_mux_set_dvi_mux()
421 W2BYTE(REG_DVI_ATOP1_06_L, 0); // enable DVI1 clock power in Hal_SC_mux_set_dvi_mux()
441 W2BYTEMSK(REG_DVI_ATOP1_06_L, 0x7FFE, 0x7FFE); // disable DVI1 clock power in Hal_SC_mux_set_dvi_mux()
454 W2BYTEMSK(REG_DVI_ATOP1_06_L, 0xFFFE, 0xFFFE); // disable DVI1 clock power in Hal_SC_mux_set_dvi_mux()
474 W2BYTEMSK(REG_DVI_ATOP1_06_L, 0x7FFE, 0x7FFE); // disable DVI1 clock power in Hal_SC_mux_set_dvi_mux()
487 W2BYTEMSK(REG_DVI_ATOP1_06_L, 0xFFFE, 0xFFFE); // disable DVI1 clock power in Hal_SC_mux_set_dvi_mux()
507 W2BYTEMSK(REG_DVI_ATOP1_06_L, 0x7FFE, 0x7FFE); // disable DVI1 clock power in Hal_SC_mux_set_dvi_mux()
520 W2BYTEMSK(REG_DVI_ATOP1_06_L, 0xFFFE, 0xFFFE); // disable DVI1 clock power in Hal_SC_mux_set_dvi_mux()
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| H A D | mhal_offline.c | 395 MS_U16 u16DVIATOP_06 = R2BYTE(REG_DVI_ATOP1_06_L); in Hal_XC_GetOffLineOfDVI1()
399 W2BYTE(REG_DVI_ATOP1_06_L, 0); // enable DVI1 clock power in Hal_XC_GetOffLineOfDVI1()
416 W2BYTE(REG_DVI_ATOP1_06_L, u16DVIATOP_06); in Hal_XC_GetOffLineOfDVI1()
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| H A D | mhal_hdmi.c | 1089 W2BYTE(REG_DVI_ATOP1_06_L, 0x0000); // enable DVI1 all clock power in Hal_HDMI_init()
1149 W2BYTEMSK(REG_DVI_ATOP1_06_L, 0x0000, 0x8001); in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/cec/include/ |
| H A D | cec_hwreg.h | 147 #define REG_DVI_ATOP1_06_L (REG_DVI_ATOP1_BASE + 0x0C) macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/cec/include/ |
| H A D | cec_hwreg.h | 147 #define REG_DVI_ATOP1_06_L (REG_DVI_ATOP1_BASE + 0x0C) macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/cec/include/ |
| H A D | cec_hwreg.h | 147 #define REG_DVI_ATOP1_06_L (REG_DVI_ATOP1_BASE + 0x0C) macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/cec/include/ |
| H A D | cec_hwreg.h | 144 #define REG_DVI_ATOP1_06_L (REG_DVI_ATOP1_BASE + 0x0C) macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/cec/include/ |
| H A D | cec_hwreg.h | 147 #define REG_DVI_ATOP1_06_L (REG_DVI_ATOP1_BASE + 0x0C) macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/cec/include/ |
| H A D | cec_hwreg.h | 147 #define REG_DVI_ATOP1_06_L (REG_DVI_ATOP1_BASE + 0x0C) macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/cec/include/ |
| H A D | cec_hwreg.h | 147 #define REG_DVI_ATOP1_06_L (REG_DVI_ATOP1_BASE + 0x0C) macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/cec/include/ |
| H A D | cec_hwreg.h | 147 #define REG_DVI_ATOP1_06_L (REG_DVI_ATOP1_BASE + 0x0C) macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/cec/include/ |
| H A D | cec_hwreg.h | 147 #define REG_DVI_ATOP1_06_L (REG_DVI_ATOP1_BASE + 0x0C) macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/cec/include/ |
| H A D | cec_hwreg.h | 144 #define REG_DVI_ATOP1_06_L (REG_DVI_ATOP1_BASE + 0x0C) macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/cec/include/ |
| H A D | cec_hwreg.h | 147 #define REG_DVI_ATOP1_06_L (REG_DVI_ATOP1_BASE + 0x0C) macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/cec/include/ |
| H A D | cec_hwreg.h | 147 #define REG_DVI_ATOP1_06_L (REG_DVI_ATOP1_BASE + 0x0C) macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/cec/include/ |
| H A D | cec_hwreg.h | 147 #define REG_DVI_ATOP1_06_L (REG_DVI_ATOP1_BASE + 0x0C) macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/cec/include/ |
| H A D | cec_hwreg.h | 147 #define REG_DVI_ATOP1_06_L (REG_DVI_ATOP1_BASE + 0x0C) macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/cec/include/ |
| H A D | cec_hwreg.h | 147 #define REG_DVI_ATOP1_06_L (REG_DVI_ATOP1_BASE + 0x0C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/ |
| H A D | hwreg_hdmi.h | 795 #define REG_DVI_ATOP1_06_L (REG_DVI_ATOP1_BASE + 0x0C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/ |
| H A D | hwreg_hdmi.h | 795 #define REG_DVI_ATOP1_06_L (REG_DVI_ATOP1_BASE + 0x0C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 787 #define REG_DVI_ATOP1_06_L (REG_DVI_ATOP1_BASE + 0x0C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 787 #define REG_DVI_ATOP1_06_L (REG_DVI_ATOP1_BASE + 0x0C) macro
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