Searched refs:REG_DSCMB_BANK (Results 1 – 11 of 11) sorted by relevance
201 #define REG_DSCMB_BANK 0x0600UL macro203 #define REG_DSCMB_CTRL (REG_DSCMB_BANK+ 0x0000UL) // ESA + CSA control221 #define REG_DSCMB_CTRL1 (REG_DSCMB_BANK+ 0x0001UL)231 #define REG_DSCMB_SCMB_TS (REG_DSCMB_BANK+ 0x0002UL)232 #define REG_DSCMB_SCMB_PES (REG_DSCMB_BANK+ 0x0004UL)233 #define REG_DSCMB_SCMB_CSA (REG_DSCMB_BANK+ 0x0006UL)235 #define REG_DSCMB_CIPHER_CONNECT_L (REG_DSCMB_BANK + 0x000AUL)242 #define REG_DSCMB0_HDCP2_RIV0 (REG_DSCMB_BANK + 0x0010UL)243 #define REG_DSCMB0_HDCP2_RIV1 (REG_DSCMB_BANK + 0x0011UL)244 #define REG_DSCMB0_HDCP2_RIV2 (REG_DSCMB_BANK + 0x0012UL)[all …]
184 #define REG_DSCMB_BANK 0x0600UL macro186 #define REG_DSCMB_CTRL (REG_DSCMB_BANK+ 0x0000UL) // ESA + CSA control204 #define REG_DSCMB_CTRL1 (REG_DSCMB_BANK+ 0x0001UL)210 #define REG_DSCMB_SCMB_TS (REG_DSCMB_BANK+ 0x0002UL)211 #define REG_DSCMB_SCMB_PES (REG_DSCMB_BANK+ 0x0004UL)213 #define REG_DSCMB0_HDCP2_RIV0 (REG_DSCMB_BANK + 0x0010UL)214 #define REG_DSCMB0_HDCP2_RIV1 (REG_DSCMB_BANK + 0x0011UL)215 #define REG_DSCMB0_HDCP2_RIV2 (REG_DSCMB_BANK + 0x0012UL)216 #define REG_DSCMB0_HDCP2_RIV3 (REG_DSCMB_BANK + 0x0013UL)217 #define REG_DSCMB1_HDCP2_RIV0 (REG_DSCMB_BANK + 0x0014UL)[all …]
216 #define REG_DSCMB_BANK 0x0600UL macro218 #define REG_DSCMB_CTRL (REG_DSCMB_BANK+ 0x0000UL) // ESA + CSA control230 #define REG_DSCMB_CTRL1 (REG_DSCMB_BANK+ 0x0001UL)236 #define REG_DSCMB_SCMB_TS (REG_DSCMB_BANK+ 0x0002UL)239 #define REG_DSCMB0_HDCP2_RIV0 (REG_DSCMB_BANK + 0x0010UL)240 #define REG_DSCMB0_HDCP2_RIV1 (REG_DSCMB_BANK + 0x0011UL)241 #define REG_DSCMB0_HDCP2_RIV2 (REG_DSCMB_BANK + 0x0012UL)242 #define REG_DSCMB0_HDCP2_RIV3 (REG_DSCMB_BANK + 0x0013UL)243 #define REG_DSCMB1_HDCP2_RIV0 (REG_DSCMB_BANK + 0x0014UL)244 #define REG_DSCMB1_HDCP2_RIV1 (REG_DSCMB_BANK + 0x0015UL)[all …]
215 #define REG_DSCMB_BANK 0x0600UL macro217 #define REG_DSCMB_CTRL (REG_DSCMB_BANK+ 0x0000UL) // ESA + CSA control229 #define REG_DSCMB_CTRL1 (REG_DSCMB_BANK+ 0x0001UL)235 #define REG_DSCMB_SCMB_TS (REG_DSCMB_BANK+ 0x0002UL)238 #define REG_DSCMB0_HDCP2_RIV0 (REG_DSCMB_BANK + 0x0010UL)239 #define REG_DSCMB0_HDCP2_RIV1 (REG_DSCMB_BANK + 0x0011UL)240 #define REG_DSCMB0_HDCP2_RIV2 (REG_DSCMB_BANK + 0x0012UL)241 #define REG_DSCMB0_HDCP2_RIV3 (REG_DSCMB_BANK + 0x0013UL)242 #define REG_DSCMB1_HDCP2_RIV0 (REG_DSCMB_BANK + 0x0014UL)243 #define REG_DSCMB1_HDCP2_RIV1 (REG_DSCMB_BANK + 0x0015UL)[all …]
148 #define REG_DSCMB_BANK 0x0600UL macro150 #define REG_DSCMB_CTRL (REG_DSCMB_BANK+ 0x0000UL)157 #define REG_DSCMB_CTRL1 (REG_DSCMB_BANK+ 0x0001UL)162 #define REG_DSCMB_SCMB_TS (REG_DSCMB_BANK+ 0x0002UL)166 #define REG_DSCMB_CIPHER_CONNECT_L (REG_DSCMB_BANK+ 0x000aUL)180 #define REG_DSCMB_KL_CTRL1 (REG_DSCMB_BANK+ 0x000cUL)197 #define REG_DSCMB_KL_CTRL2 (REG_DSCMB_BANK+ 0x000dUL)209 #define REG_DSCMB_KL_CTRL3 (REG_DSCMB_BANK+ 0x000eUL)213 #define REG_DSCMB_KL_STATUS (REG_DSCMB_BANK+ 0x000fUL)218 #define REG_DSCMB_CIPHER0_HDCP2_RIV0 (REG_DSCMB_BANK + 0x0010UL)[all …]
232 #define REG_DSCMB_BANK 0x0600UL macro234 #define REG_DSCMB_CTRL (REG_DSCMB_BANK+ 0x0000UL) // ESA + CSA control246 #define REG_DSCMB_CTRL1 (REG_DSCMB_BANK+ 0x0001UL)257 #define REG_DSCMB_SCMB_TS (REG_DSCMB_BANK+ 0x0002UL)260 #define REG_DSCMB_CIPHER_CONNECT_L (REG_DSCMB_BANK + 0x000AUL)267 #define REG_DSCMB0_HDCP2_RIV0 (REG_DSCMB_BANK + 0x0010UL)268 #define REG_DSCMB0_HDCP2_RIV1 (REG_DSCMB_BANK + 0x0011UL)269 #define REG_DSCMB0_HDCP2_RIV2 (REG_DSCMB_BANK + 0x0012UL)270 #define REG_DSCMB0_HDCP2_RIV3 (REG_DSCMB_BANK + 0x0013UL)271 #define REG_DSCMB1_HDCP2_RIV0 (REG_DSCMB_BANK + 0x0014UL)[all …]
231 #define REG_DSCMB_BANK 0x0600UL macro233 #define REG_DSCMB_CTRL (REG_DSCMB_BANK+ 0x0000UL) // ESA + CSA control245 #define REG_DSCMB_CTRL1 (REG_DSCMB_BANK+ 0x0001UL)256 #define REG_DSCMB_SCMB_TS (REG_DSCMB_BANK+ 0x0002UL)259 #define REG_DSCMB_CIPHER_CONNECT_L (REG_DSCMB_BANK + 0x000AUL)266 #define REG_DSCMB0_HDCP2_RIV0 (REG_DSCMB_BANK + 0x0010UL)267 #define REG_DSCMB0_HDCP2_RIV1 (REG_DSCMB_BANK + 0x0011UL)268 #define REG_DSCMB0_HDCP2_RIV2 (REG_DSCMB_BANK + 0x0012UL)269 #define REG_DSCMB0_HDCP2_RIV3 (REG_DSCMB_BANK + 0x0013UL)270 #define REG_DSCMB1_HDCP2_RIV0 (REG_DSCMB_BANK + 0x0014UL)[all …]