| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_hdmi.c | 1381 W2BYTEMSK(REG_COMBO_PHY1_P3_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1382 W2BYTEMSK(REG_COMBO_PHY1_P3_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5309 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_41_L; break; in Hal_DVI_irq_forcemode()
5329 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_hdmi.c | 1411 W2BYTEMSK(REG_COMBO_PHY1_P3_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1412 W2BYTEMSK(REG_COMBO_PHY1_P3_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5409 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_41_L; break; in Hal_DVI_irq_forcemode()
5429 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 1446 W2BYTEMSK(REG_COMBO_PHY1_P3_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1447 W2BYTEMSK(REG_COMBO_PHY1_P3_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5451 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_41_L; break; in Hal_DVI_irq_forcemode()
5471 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_hdmi.c | 1411 W2BYTEMSK(REG_COMBO_PHY1_P3_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1412 W2BYTEMSK(REG_COMBO_PHY1_P3_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5409 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_41_L; break; in Hal_DVI_irq_forcemode()
5429 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 1453 W2BYTEMSK(REG_COMBO_PHY1_P3_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1454 W2BYTEMSK(REG_COMBO_PHY1_P3_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5424 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_41_L; break; in Hal_DVI_irq_forcemode()
5444 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 1446 W2BYTEMSK(REG_COMBO_PHY1_P3_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1447 W2BYTEMSK(REG_COMBO_PHY1_P3_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5451 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_41_L; break; in Hal_DVI_irq_forcemode()
5471 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_hdmi.c | 1384 W2BYTEMSK(REG_COMBO_PHY1_P3_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1385 W2BYTEMSK(REG_COMBO_PHY1_P3_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
6012 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_41_L; break; in Hal_DVI_irq_forcemode()
6032 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_hdmi.c | 1384 W2BYTEMSK(REG_COMBO_PHY1_P3_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1385 W2BYTEMSK(REG_COMBO_PHY1_P3_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
6015 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_41_L; break; in Hal_DVI_irq_forcemode()
6035 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 1546 W2BYTEMSK(REG_COMBO_PHY1_P3_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1547 W2BYTEMSK(REG_COMBO_PHY1_P3_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5722 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_41_L; break; in Hal_DVI_irq_forcemode()
5742 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_hdmi.c | 1384 W2BYTEMSK(REG_COMBO_PHY1_P3_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1385 W2BYTEMSK(REG_COMBO_PHY1_P3_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
6018 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_41_L; break; in Hal_DVI_irq_forcemode()
6038 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 1546 W2BYTEMSK(REG_COMBO_PHY1_P3_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1547 W2BYTEMSK(REG_COMBO_PHY1_P3_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5722 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_41_L; break; in Hal_DVI_irq_forcemode()
5742 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 3433 #define REG_COMBO_PHY1_P3_41_L (REG_COMBO_PHY1_P3_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 3435 #define REG_COMBO_PHY1_P3_41_L (REG_COMBO_PHY1_P3_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_hdmi.h | 3433 #define REG_COMBO_PHY1_P3_41_L (REG_COMBO_PHY1_P3_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_hdmi.h | 3435 #define REG_COMBO_PHY1_P3_41_L (REG_COMBO_PHY1_P3_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_hdmi.h | 3433 #define REG_COMBO_PHY1_P3_41_L (REG_COMBO_PHY1_P3_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_hdmi.h | 3435 #define REG_COMBO_PHY1_P3_41_L (REG_COMBO_PHY1_P3_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_hdmi.h | 3435 #define REG_COMBO_PHY1_P3_41_L (REG_COMBO_PHY1_P3_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_hdmi.h | 3433 #define REG_COMBO_PHY1_P3_41_L (REG_COMBO_PHY1_P3_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_hdmi.h | 3434 #define REG_COMBO_PHY1_P3_41_L (REG_COMBO_PHY1_P3_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_hdmi.h | 3433 #define REG_COMBO_PHY1_P3_41_L (REG_COMBO_PHY1_P3_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_hdmi.h | 3433 #define REG_COMBO_PHY1_P3_41_L (REG_COMBO_PHY1_P3_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_hdmi.h | 3433 #define REG_COMBO_PHY1_P3_41_L (REG_COMBO_PHY1_P3_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/ |
| H A D | hwreg_hdmi.h | 3433 #define REG_COMBO_PHY1_P3_41_L (REG_COMBO_PHY1_P3_BASE + 0x82) macro
|