Home
last modified time | relevance | path

Searched refs:REG_COMBO_PHY1_P3_40_L (Results 1 – 24 of 24) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c1377 if(R2BYTE(REG_COMBO_PHY1_P3_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5269 case INPUT_PORT_DVI3: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P3_40_L, irqbit); break; in Hal_DVI_irq_info()
5289 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c1407 if(R2BYTE(REG_COMBO_PHY1_P3_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5369 case INPUT_PORT_DVI3: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P3_40_L, irqbit); break; in Hal_DVI_irq_info()
5389 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c1442 if(R2BYTE(REG_COMBO_PHY1_P3_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5411 case INPUT_PORT_DVI3: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P3_40_L, irqbit); break; in Hal_DVI_irq_info()
5431 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c1407 if(R2BYTE(REG_COMBO_PHY1_P3_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5369 case INPUT_PORT_DVI3: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P3_40_L, irqbit); break; in Hal_DVI_irq_info()
5389 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c1449 if(R2BYTE(REG_COMBO_PHY1_P3_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5384 case INPUT_PORT_DVI3: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P3_40_L, irqbit); break; in Hal_DVI_irq_info()
5404 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c1442 if(R2BYTE(REG_COMBO_PHY1_P3_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5411 case INPUT_PORT_DVI3: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P3_40_L, irqbit); break; in Hal_DVI_irq_info()
5431 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c1380 if(R2BYTE(REG_COMBO_PHY1_P3_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5972 case INPUT_PORT_DVI3: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P3_40_L, irqbit); break; in Hal_DVI_irq_info()
5992 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c1380 if(R2BYTE(REG_COMBO_PHY1_P3_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5975 case INPUT_PORT_DVI3: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P3_40_L, irqbit); break; in Hal_DVI_irq_info()
5995 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c1542 if(R2BYTE(REG_COMBO_PHY1_P3_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5682 case INPUT_PORT_DVI3: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P3_40_L, irqbit); break; in Hal_DVI_irq_info()
5702 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c1380 if(R2BYTE(REG_COMBO_PHY1_P3_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5978 case INPUT_PORT_DVI3: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P3_40_L, irqbit); break; in Hal_DVI_irq_info()
5998 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c1542 if(R2BYTE(REG_COMBO_PHY1_P3_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5682 case INPUT_PORT_DVI3: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P3_40_L, irqbit); break; in Hal_DVI_irq_info()
5702 case INPUT_PORT_DVI3: u16reg_add = REG_COMBO_PHY1_P3_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h3431 #define REG_COMBO_PHY1_P3_40_L (REG_COMBO_PHY1_P3_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h3433 #define REG_COMBO_PHY1_P3_40_L (REG_COMBO_PHY1_P3_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h3431 #define REG_COMBO_PHY1_P3_40_L (REG_COMBO_PHY1_P3_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h3433 #define REG_COMBO_PHY1_P3_40_L (REG_COMBO_PHY1_P3_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h3431 #define REG_COMBO_PHY1_P3_40_L (REG_COMBO_PHY1_P3_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h3433 #define REG_COMBO_PHY1_P3_40_L (REG_COMBO_PHY1_P3_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h3433 #define REG_COMBO_PHY1_P3_40_L (REG_COMBO_PHY1_P3_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h3431 #define REG_COMBO_PHY1_P3_40_L (REG_COMBO_PHY1_P3_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h3432 #define REG_COMBO_PHY1_P3_40_L (REG_COMBO_PHY1_P3_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h3431 #define REG_COMBO_PHY1_P3_40_L (REG_COMBO_PHY1_P3_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h3431 #define REG_COMBO_PHY1_P3_40_L (REG_COMBO_PHY1_P3_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h3431 #define REG_COMBO_PHY1_P3_40_L (REG_COMBO_PHY1_P3_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h3431 #define REG_COMBO_PHY1_P3_40_L (REG_COMBO_PHY1_P3_BASE + 0x80) macro