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Searched refs:REG_COMBO_PHY1_P2_04_L (Results 1 – 24 of 24) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c921 W2BYTEMSK(REG_COMBO_PHY1_P2_04_L, 0, BIT(12)); // reg_atop_gc_ictrl_pfd_h_ov in _Hal_tmds_EQBandWidthSetting()
3108 W2BYTEMSK(REG_COMBO_PHY1_P2_04_L, BIT(8), BMASK(9:8)); in _Hal_tmds_EQCalibrationProc()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c932 W2BYTEMSK(REG_COMBO_PHY1_P2_04_L, 0, BIT(12)); // reg_atop_gc_ictrl_pfd_h_ov in _Hal_tmds_EQBandWidthSetting()
3145 W2BYTEMSK(REG_COMBO_PHY1_P2_04_L, BIT(8), BMASK(9:8)); in _Hal_tmds_EQCalibrationProc()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c932 W2BYTEMSK(REG_COMBO_PHY1_P2_04_L, 0, BIT(12)); // reg_atop_gc_ictrl_pfd_h_ov in _Hal_tmds_EQBandWidthSetting()
3145 W2BYTEMSK(REG_COMBO_PHY1_P2_04_L, BIT(8), BMASK(9:8)); in _Hal_tmds_EQCalibrationProc()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c993 W2BYTEMSK(REG_COMBO_PHY1_P2_04_L, 0, BIT(12)); // reg_atop_gc_ictrl_pfd_h_ov in _Hal_tmds_EQBandWidthSetting()
3145 W2BYTEMSK(REG_COMBO_PHY1_P2_04_L, BIT(8), BMASK(9:8)); in _Hal_tmds_EQCalibrationProc()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c924 W2BYTEMSK(REG_COMBO_PHY1_P2_04_L, 0, BIT(12)); // reg_atop_gc_ictrl_pfd_h_ov in _Hal_tmds_EQBandWidthSetting()
3136 W2BYTEMSK(REG_COMBO_PHY1_P2_04_L, BIT(8), BMASK(9:8)); in _Hal_tmds_EQCalibrationProc()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c924 W2BYTEMSK(REG_COMBO_PHY1_P2_04_L, 0, BIT(12)); // reg_atop_gc_ictrl_pfd_h_ov in _Hal_tmds_EQBandWidthSetting()
3139 W2BYTEMSK(REG_COMBO_PHY1_P2_04_L, BIT(8), BMASK(9:8)); in _Hal_tmds_EQCalibrationProc()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c1059 W2BYTEMSK(REG_COMBO_PHY1_P2_04_L, 0, BIT(12)); // reg_atop_gc_ictrl_pfd_h_ov in _Hal_tmds_EQBandWidthSetting()
3310 W2BYTEMSK(REG_COMBO_PHY1_P2_04_L, BIT(8), BMASK(9:8)); in _Hal_tmds_EQCalibrationProc()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c924 W2BYTEMSK(REG_COMBO_PHY1_P2_04_L, 0, BIT(12)); // reg_atop_gc_ictrl_pfd_h_ov in _Hal_tmds_EQBandWidthSetting()
3139 W2BYTEMSK(REG_COMBO_PHY1_P2_04_L, BIT(8), BMASK(9:8)); in _Hal_tmds_EQCalibrationProc()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c1059 W2BYTEMSK(REG_COMBO_PHY1_P2_04_L, 0, BIT(12)); // reg_atop_gc_ictrl_pfd_h_ov in _Hal_tmds_EQBandWidthSetting()
3310 W2BYTEMSK(REG_COMBO_PHY1_P2_04_L, BIT(8), BMASK(9:8)); in _Hal_tmds_EQCalibrationProc()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c3137 W2BYTEMSK(REG_COMBO_PHY1_P2_04_L, BIT(8), BMASK(9:8)); in _Hal_tmds_EQCalibrationProc()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c3137 W2BYTEMSK(REG_COMBO_PHY1_P2_04_L, BIT(8), BMASK(9:8)); in _Hal_tmds_EQCalibrationProc()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h2795 #define REG_COMBO_PHY1_P2_04_L (REG_COMBO_PHY1_P2_BASE + 0x08) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h2797 #define REG_COMBO_PHY1_P2_04_L (REG_COMBO_PHY1_P2_BASE + 0x08) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h2795 #define REG_COMBO_PHY1_P2_04_L (REG_COMBO_PHY1_P2_BASE + 0x08) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h2797 #define REG_COMBO_PHY1_P2_04_L (REG_COMBO_PHY1_P2_BASE + 0x08) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h2795 #define REG_COMBO_PHY1_P2_04_L (REG_COMBO_PHY1_P2_BASE + 0x08) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h2797 #define REG_COMBO_PHY1_P2_04_L (REG_COMBO_PHY1_P2_BASE + 0x08) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h2797 #define REG_COMBO_PHY1_P2_04_L (REG_COMBO_PHY1_P2_BASE + 0x08) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h2795 #define REG_COMBO_PHY1_P2_04_L (REG_COMBO_PHY1_P2_BASE + 0x08) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h2796 #define REG_COMBO_PHY1_P2_04_L (REG_COMBO_PHY1_P2_BASE + 0x08) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h2795 #define REG_COMBO_PHY1_P2_04_L (REG_COMBO_PHY1_P2_BASE + 0x08) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h2795 #define REG_COMBO_PHY1_P2_04_L (REG_COMBO_PHY1_P2_BASE + 0x08) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h2795 #define REG_COMBO_PHY1_P2_04_L (REG_COMBO_PHY1_P2_BASE + 0x08) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h2795 #define REG_COMBO_PHY1_P2_04_L (REG_COMBO_PHY1_P2_BASE + 0x08) macro