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Searched refs:REG_COMBO_PHY1_P1_40_L (Results 1 – 24 of 24) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c1355 if(R2BYTE(REG_COMBO_PHY1_P1_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5267 case INPUT_PORT_DVI1: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P1_40_L, irqbit); break; in Hal_DVI_irq_info()
5287 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c1385 if(R2BYTE(REG_COMBO_PHY1_P1_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5367 case INPUT_PORT_DVI1: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P1_40_L, irqbit); break; in Hal_DVI_irq_info()
5387 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c1420 if(R2BYTE(REG_COMBO_PHY1_P1_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5409 case INPUT_PORT_DVI1: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P1_40_L, irqbit); break; in Hal_DVI_irq_info()
5429 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c1385 if(R2BYTE(REG_COMBO_PHY1_P1_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5367 case INPUT_PORT_DVI1: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P1_40_L, irqbit); break; in Hal_DVI_irq_info()
5387 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c1427 if(R2BYTE(REG_COMBO_PHY1_P1_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5382 case INPUT_PORT_DVI1: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P1_40_L, irqbit); break; in Hal_DVI_irq_info()
5402 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c1420 if(R2BYTE(REG_COMBO_PHY1_P1_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5409 case INPUT_PORT_DVI1: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P1_40_L, irqbit); break; in Hal_DVI_irq_info()
5429 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c1358 if(R2BYTE(REG_COMBO_PHY1_P1_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5970 case INPUT_PORT_DVI1: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P1_40_L, irqbit); break; in Hal_DVI_irq_info()
5990 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c1358 if(R2BYTE(REG_COMBO_PHY1_P1_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5973 case INPUT_PORT_DVI1: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P1_40_L, irqbit); break; in Hal_DVI_irq_info()
5993 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c1520 if(R2BYTE(REG_COMBO_PHY1_P1_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5680 case INPUT_PORT_DVI1: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P1_40_L, irqbit); break; in Hal_DVI_irq_info()
5700 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c1358 if(R2BYTE(REG_COMBO_PHY1_P1_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5976 case INPUT_PORT_DVI1: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P1_40_L, irqbit); break; in Hal_DVI_irq_info()
5996 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c1520 if(R2BYTE(REG_COMBO_PHY1_P1_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5680 case INPUT_PORT_DVI1: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P1_40_L, irqbit); break; in Hal_DVI_irq_info()
5700 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h2399 #define REG_COMBO_PHY1_P1_40_L (REG_COMBO_PHY1_P1_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h2401 #define REG_COMBO_PHY1_P1_40_L (REG_COMBO_PHY1_P1_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h2399 #define REG_COMBO_PHY1_P1_40_L (REG_COMBO_PHY1_P1_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h2401 #define REG_COMBO_PHY1_P1_40_L (REG_COMBO_PHY1_P1_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h2399 #define REG_COMBO_PHY1_P1_40_L (REG_COMBO_PHY1_P1_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h2401 #define REG_COMBO_PHY1_P1_40_L (REG_COMBO_PHY1_P1_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h2401 #define REG_COMBO_PHY1_P1_40_L (REG_COMBO_PHY1_P1_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h2399 #define REG_COMBO_PHY1_P1_40_L (REG_COMBO_PHY1_P1_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h2400 #define REG_COMBO_PHY1_P1_40_L (REG_COMBO_PHY1_P1_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h2399 #define REG_COMBO_PHY1_P1_40_L (REG_COMBO_PHY1_P1_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h2399 #define REG_COMBO_PHY1_P1_40_L (REG_COMBO_PHY1_P1_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h2399 #define REG_COMBO_PHY1_P1_40_L (REG_COMBO_PHY1_P1_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h2399 #define REG_COMBO_PHY1_P1_40_L (REG_COMBO_PHY1_P1_BASE + 0x80) macro