| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_hdmi.c | 559 W2BYTEMSK(REG_COMBO_PHY1_P0_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
560 W2BYTEMSK(REG_COMBO_PHY1_P0_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
2959 u16reg_add = REG_COMBO_PHY1_P0_41_L; in Hal_DVI_irq_forcemode()
2981 u16reg_add = REG_COMBO_PHY1_P0_41_L; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_hdmi.c | 731 W2BYTEMSK(REG_COMBO_PHY1_P0_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
732 W2BYTEMSK(REG_COMBO_PHY1_P0_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
3696 u16reg_add = REG_COMBO_PHY1_P0_41_L; in Hal_DVI_irq_forcemode()
3718 u16reg_add = REG_COMBO_PHY1_P0_41_L; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_hdmi.c | 1348 W2BYTEMSK(REG_COMBO_PHY1_P0_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1349 W2BYTEMSK(REG_COMBO_PHY1_P0_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5306 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_41_L; break; in Hal_DVI_irq_forcemode()
5326 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_hdmi.c | 1359 W2BYTEMSK(REG_COMBO_PHY1_P0_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1360 W2BYTEMSK(REG_COMBO_PHY1_P0_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5406 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_41_L; break; in Hal_DVI_irq_forcemode()
5426 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 1413 W2BYTEMSK(REG_COMBO_PHY1_P0_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1414 W2BYTEMSK(REG_COMBO_PHY1_P0_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5448 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_41_L; break; in Hal_DVI_irq_forcemode()
5468 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_hdmi.c | 1359 W2BYTEMSK(REG_COMBO_PHY1_P0_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1360 W2BYTEMSK(REG_COMBO_PHY1_P0_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5406 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_41_L; break; in Hal_DVI_irq_forcemode()
5426 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 1420 W2BYTEMSK(REG_COMBO_PHY1_P0_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1421 W2BYTEMSK(REG_COMBO_PHY1_P0_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5421 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_41_L; break; in Hal_DVI_irq_forcemode()
5441 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 1413 W2BYTEMSK(REG_COMBO_PHY1_P0_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1414 W2BYTEMSK(REG_COMBO_PHY1_P0_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5448 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_41_L; break; in Hal_DVI_irq_forcemode()
5468 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_hdmi.c | 1351 W2BYTEMSK(REG_COMBO_PHY1_P0_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1352 W2BYTEMSK(REG_COMBO_PHY1_P0_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
6009 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_41_L; break; in Hal_DVI_irq_forcemode()
6029 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_hdmi.c | 1351 W2BYTEMSK(REG_COMBO_PHY1_P0_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1352 W2BYTEMSK(REG_COMBO_PHY1_P0_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
6012 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_41_L; break; in Hal_DVI_irq_forcemode()
6032 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 1513 W2BYTEMSK(REG_COMBO_PHY1_P0_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1514 W2BYTEMSK(REG_COMBO_PHY1_P0_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5719 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_41_L; break; in Hal_DVI_irq_forcemode()
5739 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_hdmi.c | 1351 W2BYTEMSK(REG_COMBO_PHY1_P0_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1352 W2BYTEMSK(REG_COMBO_PHY1_P0_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
6015 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_41_L; break; in Hal_DVI_irq_forcemode()
6035 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 1513 W2BYTEMSK(REG_COMBO_PHY1_P0_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1514 W2BYTEMSK(REG_COMBO_PHY1_P0_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5719 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_41_L; break; in Hal_DVI_irq_forcemode()
5739 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 1885 #define REG_COMBO_PHY1_P0_41_L (REG_COMBO_PHY1_P0_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 1887 #define REG_COMBO_PHY1_P0_41_L (REG_COMBO_PHY1_P0_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_hdmi.h | 1885 #define REG_COMBO_PHY1_P0_41_L (REG_COMBO_PHY1_P0_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_hdmi.h | 1887 #define REG_COMBO_PHY1_P0_41_L (REG_COMBO_PHY1_P0_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_hdmi.h | 1885 #define REG_COMBO_PHY1_P0_41_L (REG_COMBO_PHY1_P0_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_hdmi.h | 1887 #define REG_COMBO_PHY1_P0_41_L (REG_COMBO_PHY1_P0_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_hdmi.h | 1887 #define REG_COMBO_PHY1_P0_41_L (REG_COMBO_PHY1_P0_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_hdmi.h | 1885 #define REG_COMBO_PHY1_P0_41_L (REG_COMBO_PHY1_P0_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_hdmi.h | 1886 #define REG_COMBO_PHY1_P0_41_L (REG_COMBO_PHY1_P0_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_hdmi.h | 1885 #define REG_COMBO_PHY1_P0_41_L (REG_COMBO_PHY1_P0_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_hdmi.h | 1885 #define REG_COMBO_PHY1_P0_41_L (REG_COMBO_PHY1_P0_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_hdmi.h | 1885 #define REG_COMBO_PHY1_P0_41_L (REG_COMBO_PHY1_P0_BASE + 0x82) macro
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