| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_hdmi.c | 555 if(R2BYTE(REG_COMBO_PHY1_P0_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
2915 u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P0_40_L, irqbit); in Hal_DVI_irq_info()
2937 u16reg_add = REG_COMBO_PHY1_P0_40_L; in Hal_DVI_irq_mask()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_hdmi.c | 727 if(R2BYTE(REG_COMBO_PHY1_P0_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
3652 u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P0_40_L, irqbit); in Hal_DVI_irq_info()
3674 u16reg_add = REG_COMBO_PHY1_P0_40_L; in Hal_DVI_irq_mask()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_hdmi.c | 1344 if(R2BYTE(REG_COMBO_PHY1_P0_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5266 case INPUT_PORT_DVI0: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P0_40_L, irqbit); break; in Hal_DVI_irq_info()
5286 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_40_L; break; in Hal_DVI_irq_mask()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_hdmi.c | 1355 if(R2BYTE(REG_COMBO_PHY1_P0_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5366 case INPUT_PORT_DVI0: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P0_40_L, irqbit); break; in Hal_DVI_irq_info()
5386 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_40_L; break; in Hal_DVI_irq_mask()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 1409 if(R2BYTE(REG_COMBO_PHY1_P0_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5408 case INPUT_PORT_DVI0: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P0_40_L, irqbit); break; in Hal_DVI_irq_info()
5428 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_40_L; break; in Hal_DVI_irq_mask()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_hdmi.c | 1355 if(R2BYTE(REG_COMBO_PHY1_P0_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5366 case INPUT_PORT_DVI0: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P0_40_L, irqbit); break; in Hal_DVI_irq_info()
5386 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_40_L; break; in Hal_DVI_irq_mask()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 1416 if(R2BYTE(REG_COMBO_PHY1_P0_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5381 case INPUT_PORT_DVI0: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P0_40_L, irqbit); break; in Hal_DVI_irq_info()
5401 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_40_L; break; in Hal_DVI_irq_mask()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 1409 if(R2BYTE(REG_COMBO_PHY1_P0_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5408 case INPUT_PORT_DVI0: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P0_40_L, irqbit); break; in Hal_DVI_irq_info()
5428 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_40_L; break; in Hal_DVI_irq_mask()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_hdmi.c | 1347 if(R2BYTE(REG_COMBO_PHY1_P0_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5969 case INPUT_PORT_DVI0: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P0_40_L, irqbit); break; in Hal_DVI_irq_info()
5989 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_40_L; break; in Hal_DVI_irq_mask()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_hdmi.c | 1347 if(R2BYTE(REG_COMBO_PHY1_P0_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5972 case INPUT_PORT_DVI0: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P0_40_L, irqbit); break; in Hal_DVI_irq_info()
5992 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_40_L; break; in Hal_DVI_irq_mask()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 1509 if(R2BYTE(REG_COMBO_PHY1_P0_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5679 case INPUT_PORT_DVI0: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P0_40_L, irqbit); break; in Hal_DVI_irq_info()
5699 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_40_L; break; in Hal_DVI_irq_mask()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_hdmi.c | 1347 if(R2BYTE(REG_COMBO_PHY1_P0_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5975 case INPUT_PORT_DVI0: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P0_40_L, irqbit); break; in Hal_DVI_irq_info()
5995 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_40_L; break; in Hal_DVI_irq_mask()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 1509 if(R2BYTE(REG_COMBO_PHY1_P0_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5679 case INPUT_PORT_DVI0: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P0_40_L, irqbit); break; in Hal_DVI_irq_info()
5699 case INPUT_PORT_DVI0: u16reg_add = REG_COMBO_PHY1_P0_40_L; break; in Hal_DVI_irq_mask()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 1883 #define REG_COMBO_PHY1_P0_40_L (REG_COMBO_PHY1_P0_BASE + 0x80) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 1885 #define REG_COMBO_PHY1_P0_40_L (REG_COMBO_PHY1_P0_BASE + 0x80) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_hdmi.h | 1883 #define REG_COMBO_PHY1_P0_40_L (REG_COMBO_PHY1_P0_BASE + 0x80) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_hdmi.h | 1885 #define REG_COMBO_PHY1_P0_40_L (REG_COMBO_PHY1_P0_BASE + 0x80) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_hdmi.h | 1883 #define REG_COMBO_PHY1_P0_40_L (REG_COMBO_PHY1_P0_BASE + 0x80) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_hdmi.h | 1885 #define REG_COMBO_PHY1_P0_40_L (REG_COMBO_PHY1_P0_BASE + 0x80) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_hdmi.h | 1885 #define REG_COMBO_PHY1_P0_40_L (REG_COMBO_PHY1_P0_BASE + 0x80) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_hdmi.h | 1883 #define REG_COMBO_PHY1_P0_40_L (REG_COMBO_PHY1_P0_BASE + 0x80) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_hdmi.h | 1884 #define REG_COMBO_PHY1_P0_40_L (REG_COMBO_PHY1_P0_BASE + 0x80) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_hdmi.h | 1883 #define REG_COMBO_PHY1_P0_40_L (REG_COMBO_PHY1_P0_BASE + 0x80) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_hdmi.h | 1883 #define REG_COMBO_PHY1_P0_40_L (REG_COMBO_PHY1_P0_BASE + 0x80) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_hdmi.h | 1883 #define REG_COMBO_PHY1_P0_40_L (REG_COMBO_PHY1_P0_BASE + 0x80) macro
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