Home
last modified time | relevance | path

Searched refs:REG_COMBO_PHY1_P0_00_L (Results 1 – 25 of 35) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_mux.c325 W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
348 W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
371 W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
394 W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
417 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c1893 W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_mux.c334 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
368 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
402 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
436 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
469 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c4010 …W2BYTE(REG_COMBO_PHY1_P0_00_L + u16bank_offset, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_p… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_mux.c325 W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
349 W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
373 W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
397 W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
421 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c2628 W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_mux.c334 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
368 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
402 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
436 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
469 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c4692 …W2BYTE(REG_COMBO_PHY1_P0_00_L + u16bank_offset, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_p… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_mux.c334 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
368 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
402 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
436 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
469 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c4689 …W2BYTE(REG_COMBO_PHY1_P0_00_L + u16bank_offset, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_p… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_mux.c334 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
368 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
402 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
436 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
469 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c4246 …W2BYTE(REG_COMBO_PHY1_P0_00_L + u16bank_offset, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_p… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_mux.c334 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
368 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
402 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
436 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
469 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c4246 …W2BYTE(REG_COMBO_PHY1_P0_00_L + u16bank_offset, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_p… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_mux.c334 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
368 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
402 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
436 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
469 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c4686 …W2BYTE(REG_COMBO_PHY1_P0_00_L + u16bank_offset, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_p… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_mux.c334 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
368 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
402 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
436 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
469 … W2BYTE(REG_COMBO_PHY1_P0_00_L, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_pd_osc in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c4055 …W2BYTE(REG_COMBO_PHY1_P0_00_L + u16bank_offset, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_p… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c4115 …W2BYTE(REG_COMBO_PHY1_P0_00_L + u16bank_offset, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_p… in Hal_HDMI_init()
4184 …W2BYTE(REG_COMBO_PHY1_P0_00_L + u16bank_offset, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_p… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c4115 …W2BYTE(REG_COMBO_PHY1_P0_00_L + u16bank_offset, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_p… in Hal_HDMI_init()
4184 …W2BYTE(REG_COMBO_PHY1_P0_00_L + u16bank_offset, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_p… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c4124 …W2BYTE(REG_COMBO_PHY1_P0_00_L + u16bank_offset, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_p… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c4124 …W2BYTE(REG_COMBO_PHY1_P0_00_L + u16bank_offset, 0x0007);// [3]: reg_atop_pd_ldo; [2:0]: reg_atop_p… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h1755 #define REG_COMBO_PHY1_P0_00_L (REG_COMBO_PHY1_P0_BASE + 0x00) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h1757 #define REG_COMBO_PHY1_P0_00_L (REG_COMBO_PHY1_P0_BASE + 0x00) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h1755 #define REG_COMBO_PHY1_P0_00_L (REG_COMBO_PHY1_P0_BASE + 0x00) macro

12