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Searched refs:REG_COMBO_PHY0_P3_7E_L (Results 1 – 24 of 24) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c3180 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3181 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3192 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3193 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3195 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3200 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3203 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3204 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3206 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3211 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c3217 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3218 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3229 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3230 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3232 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3237 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3240 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3241 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3243 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3248 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c3209 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3210 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3221 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3222 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3224 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3229 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3232 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3233 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3235 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3240 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c3217 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3218 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3229 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3230 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3232 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3237 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3240 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3241 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3243 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3248 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c3217 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3218 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3229 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3230 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3232 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3237 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3240 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3241 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3243 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3248 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c3209 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3210 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3221 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3222 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3224 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3229 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3232 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3233 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3235 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3240 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c3208 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3209 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3220 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3221 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3223 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3228 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3231 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3232 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3234 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3239 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c3211 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3212 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3223 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3224 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3226 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3231 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3234 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3235 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3237 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3242 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c3382 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3383 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3394 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3395 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3397 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3402 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3405 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3406 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3408 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3413 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c3211 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3212 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3223 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3224 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3226 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3231 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3234 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3235 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3237 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3242 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c3382 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3383 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3394 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3395 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3397 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3402 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3405 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3406 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3408 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3413 W2BYTEMSK(REG_COMBO_PHY0_P3_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h3297 #define REG_COMBO_PHY0_P3_7E_L (REG_COMBO_PHY0_P3_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h3299 #define REG_COMBO_PHY0_P3_7E_L (REG_COMBO_PHY0_P3_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h3297 #define REG_COMBO_PHY0_P3_7E_L (REG_COMBO_PHY0_P3_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h3299 #define REG_COMBO_PHY0_P3_7E_L (REG_COMBO_PHY0_P3_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h3297 #define REG_COMBO_PHY0_P3_7E_L (REG_COMBO_PHY0_P3_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h3299 #define REG_COMBO_PHY0_P3_7E_L (REG_COMBO_PHY0_P3_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h3299 #define REG_COMBO_PHY0_P3_7E_L (REG_COMBO_PHY0_P3_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h3297 #define REG_COMBO_PHY0_P3_7E_L (REG_COMBO_PHY0_P3_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h3298 #define REG_COMBO_PHY0_P3_7E_L (REG_COMBO_PHY0_P3_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h3297 #define REG_COMBO_PHY0_P3_7E_L (REG_COMBO_PHY0_P3_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h3297 #define REG_COMBO_PHY0_P3_7E_L (REG_COMBO_PHY0_P3_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h3297 #define REG_COMBO_PHY0_P3_7E_L (REG_COMBO_PHY0_P3_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h3297 #define REG_COMBO_PHY0_P3_7E_L (REG_COMBO_PHY0_P3_BASE + 0xFC) macro