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Searched refs:REG_COMBO_PHY0_P3_6E_L (Results 1 – 25 of 30) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/
H A DhalMHL.c489 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BIT(8), BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
2584 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, 0, BMASK(7:4)); in _mhal_mhl_MHL30AutoEQEnable()
2592 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BMASK(7:4), BMASK(7:4)); in _mhal_mhl_MHL30AutoEQEnable()
3176 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, 0, BIT(8)); in mhal_mhl_CDRModeMonitor()
3236 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BIT(8), BIT(8)); in mhal_mhl_CDRModeMonitor()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/
H A DhalMHL.c489 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BIT(8), BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
2584 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, 0, BMASK(7:4)); in _mhal_mhl_MHL30AutoEQEnable()
2592 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BMASK(7:4), BMASK(7:4)); in _mhal_mhl_MHL30AutoEQEnable()
3176 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, 0, BIT(8)); in mhal_mhl_CDRModeMonitor()
3236 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BIT(8), BIT(8)); in mhal_mhl_CDRModeMonitor()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/
H A DhalMHL.c489 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BIT(8), BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
2584 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, 0, BMASK(7:4)); in _mhal_mhl_MHL30AutoEQEnable()
2592 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BMASK(7:4), BMASK(7:4)); in _mhal_mhl_MHL30AutoEQEnable()
3176 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, 0, BIT(8)); in mhal_mhl_CDRModeMonitor()
3236 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BIT(8), BIT(8)); in mhal_mhl_CDRModeMonitor()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/
H A DhalMHL.c489 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BIT(8), BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
2584 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, 0, BMASK(7:4)); in _mhal_mhl_MHL30AutoEQEnable()
2592 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BMASK(7:4), BMASK(7:4)); in _mhal_mhl_MHL30AutoEQEnable()
3176 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, 0, BIT(8)); in mhal_mhl_CDRModeMonitor()
3236 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BIT(8), BIT(8)); in mhal_mhl_CDRModeMonitor()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/
H A DhalMHL.c489 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BIT(8), BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
2584 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, 0, BMASK(7:4)); in _mhal_mhl_MHL30AutoEQEnable()
2592 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BMASK(7:4), BMASK(7:4)); in _mhal_mhl_MHL30AutoEQEnable()
3176 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, 0, BIT(8)); in mhal_mhl_CDRModeMonitor()
3236 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BIT(8), BIT(8)); in mhal_mhl_CDRModeMonitor()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c1847 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, 0, BMASK(7:4)); in _Hal_tmds_AutoEQFunctionEnable()
1855 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BMASK(7:4), BMASK(7:4)); in _Hal_tmds_AutoEQFunctionEnable()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c1877 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, 0, BMASK(7:4)); in _Hal_tmds_AutoEQFunctionEnable()
1885 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BMASK(7:4), BMASK(7:4)); in _Hal_tmds_AutoEQFunctionEnable()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c1916 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, 0, BMASK(7:4)); in _Hal_tmds_AutoEQFunctionEnable()
1924 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BMASK(7:4), BMASK(7:4)); in _Hal_tmds_AutoEQFunctionEnable()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c1877 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, 0, BMASK(7:4)); in _Hal_tmds_AutoEQFunctionEnable()
1885 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BMASK(7:4), BMASK(7:4)); in _Hal_tmds_AutoEQFunctionEnable()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c1923 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, 0, BMASK(7:4)); in _Hal_tmds_AutoEQFunctionEnable()
1931 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BMASK(7:4), BMASK(7:4)); in _Hal_tmds_AutoEQFunctionEnable()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c1916 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, 0, BMASK(7:4)); in _Hal_tmds_AutoEQFunctionEnable()
1924 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BMASK(7:4), BMASK(7:4)); in _Hal_tmds_AutoEQFunctionEnable()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c1856 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, 0, BMASK(7:4)); in _Hal_tmds_AutoEQFunctionEnable()
1865 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BMASK(7:4), BMASK(7:4)); in _Hal_tmds_AutoEQFunctionEnable()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c1856 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, 0, BMASK(7:4)); in _Hal_tmds_AutoEQFunctionEnable()
1865 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BMASK(7:4), BMASK(7:4)); in _Hal_tmds_AutoEQFunctionEnable()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c2016 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, 0, BMASK(7:4)); in _Hal_tmds_AutoEQFunctionEnable()
2024 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BMASK(7:4), BMASK(7:4)); in _Hal_tmds_AutoEQFunctionEnable()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c1856 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, 0, BMASK(7:4)); in _Hal_tmds_AutoEQFunctionEnable()
1865 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BMASK(7:4), BMASK(7:4)); in _Hal_tmds_AutoEQFunctionEnable()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c2016 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, 0, BMASK(7:4)); in _Hal_tmds_AutoEQFunctionEnable()
2024 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BMASK(7:4), BMASK(7:4)); in _Hal_tmds_AutoEQFunctionEnable()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/mhl/internal/
H A DhalMHL.c485 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BIT(8), BIT(8)); in _mhal_mhl_HdmiBypassModeSetting()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h3265 #define REG_COMBO_PHY0_P3_6E_L (REG_COMBO_PHY0_P3_BASE + 0xDC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h3267 #define REG_COMBO_PHY0_P3_6E_L (REG_COMBO_PHY0_P3_BASE + 0xDC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h3265 #define REG_COMBO_PHY0_P3_6E_L (REG_COMBO_PHY0_P3_BASE + 0xDC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h3267 #define REG_COMBO_PHY0_P3_6E_L (REG_COMBO_PHY0_P3_BASE + 0xDC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h3265 #define REG_COMBO_PHY0_P3_6E_L (REG_COMBO_PHY0_P3_BASE + 0xDC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h3267 #define REG_COMBO_PHY0_P3_6E_L (REG_COMBO_PHY0_P3_BASE + 0xDC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h3267 #define REG_COMBO_PHY0_P3_6E_L (REG_COMBO_PHY0_P3_BASE + 0xDC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h3265 #define REG_COMBO_PHY0_P3_6E_L (REG_COMBO_PHY0_P3_BASE + 0xDC) macro

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