| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_hdmi.c | 578 W2BYTEMSK(REG_COMBO_PHY0_P3_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
579 …W2BYTEMSK(REG_COMBO_PHY0_P3_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5143 if(R2BYTE(REG_COMBO_PHY0_P3_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_hdmi.c | 586 W2BYTEMSK(REG_COMBO_PHY0_P3_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
587 …W2BYTEMSK(REG_COMBO_PHY0_P3_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5243 if(R2BYTE(REG_COMBO_PHY0_P3_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 657 W2BYTEMSK(REG_COMBO_PHY0_P3_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
658 …W2BYTEMSK(REG_COMBO_PHY0_P3_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5281 if(R2BYTE(REG_COMBO_PHY0_P3_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_hdmi.c | 586 W2BYTEMSK(REG_COMBO_PHY0_P3_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
587 …W2BYTEMSK(REG_COMBO_PHY0_P3_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5243 if(R2BYTE(REG_COMBO_PHY0_P3_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 650 W2BYTEMSK(REG_COMBO_PHY0_P3_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
651 …W2BYTEMSK(REG_COMBO_PHY0_P3_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5254 if(R2BYTE(REG_COMBO_PHY0_P3_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 657 W2BYTEMSK(REG_COMBO_PHY0_P3_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
658 …W2BYTEMSK(REG_COMBO_PHY0_P3_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5281 if(R2BYTE(REG_COMBO_PHY0_P3_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_hdmi.c | 581 W2BYTEMSK(REG_COMBO_PHY0_P3_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
582 …W2BYTEMSK(REG_COMBO_PHY0_P3_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5846 if(R2BYTE(REG_COMBO_PHY0_P3_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_hdmi.c | 581 W2BYTEMSK(REG_COMBO_PHY0_P3_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
582 …W2BYTEMSK(REG_COMBO_PHY0_P3_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5849 if(R2BYTE(REG_COMBO_PHY0_P3_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 716 W2BYTEMSK(REG_COMBO_PHY0_P3_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
717 …W2BYTEMSK(REG_COMBO_PHY0_P3_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5552 if(R2BYTE(REG_COMBO_PHY0_P3_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_hdmi.c | 581 W2BYTEMSK(REG_COMBO_PHY0_P3_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
582 …W2BYTEMSK(REG_COMBO_PHY0_P3_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5852 if(R2BYTE(REG_COMBO_PHY0_P3_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 716 W2BYTEMSK(REG_COMBO_PHY0_P3_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
717 …W2BYTEMSK(REG_COMBO_PHY0_P3_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5552 if(R2BYTE(REG_COMBO_PHY0_P3_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_hdmi.c | 2784 if(R2BYTE(REG_COMBO_PHY0_P3_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_hdmi.c | 3521 if(R2BYTE(REG_COMBO_PHY0_P3_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 3145 #define REG_COMBO_PHY0_P3_32_L (REG_COMBO_PHY0_P3_BASE + 0x64) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 3147 #define REG_COMBO_PHY0_P3_32_L (REG_COMBO_PHY0_P3_BASE + 0x64) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_hdmi.h | 3145 #define REG_COMBO_PHY0_P3_32_L (REG_COMBO_PHY0_P3_BASE + 0x64) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_hdmi.h | 3147 #define REG_COMBO_PHY0_P3_32_L (REG_COMBO_PHY0_P3_BASE + 0x64) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_hdmi.h | 3145 #define REG_COMBO_PHY0_P3_32_L (REG_COMBO_PHY0_P3_BASE + 0x64) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_hdmi.h | 3147 #define REG_COMBO_PHY0_P3_32_L (REG_COMBO_PHY0_P3_BASE + 0x64) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_hdmi.h | 3147 #define REG_COMBO_PHY0_P3_32_L (REG_COMBO_PHY0_P3_BASE + 0x64) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_hdmi.h | 3145 #define REG_COMBO_PHY0_P3_32_L (REG_COMBO_PHY0_P3_BASE + 0x64) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_hdmi.h | 3146 #define REG_COMBO_PHY0_P3_32_L (REG_COMBO_PHY0_P3_BASE + 0x64) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_hdmi.h | 3145 #define REG_COMBO_PHY0_P3_32_L (REG_COMBO_PHY0_P3_BASE + 0x64) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_hdmi.h | 3145 #define REG_COMBO_PHY0_P3_32_L (REG_COMBO_PHY0_P3_BASE + 0x64) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_hdmi.h | 3145 #define REG_COMBO_PHY0_P3_32_L (REG_COMBO_PHY0_P3_BASE + 0x64) macro
|