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Searched refs:REG_COMBO_PHY0_P3_0B_L (Results 1 – 20 of 20) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_mux.c330 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
364 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
398 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
432 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
465 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_mux.c330 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
364 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
398 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
432 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
465 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_mux.c330 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
364 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
398 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
432 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
465 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_mux.c330 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
364 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
398 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
432 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
465 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_mux.c330 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
364 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
398 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
432 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
465 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_mux.c330 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
364 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
398 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
432 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
465 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_mux.c330 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
364 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
398 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
432 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
465 W2BYTE(REG_COMBO_PHY0_P3_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h3067 #define REG_COMBO_PHY0_P3_0B_L (REG_COMBO_PHY0_P3_BASE + 0x16) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h3069 #define REG_COMBO_PHY0_P3_0B_L (REG_COMBO_PHY0_P3_BASE + 0x16) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h3067 #define REG_COMBO_PHY0_P3_0B_L (REG_COMBO_PHY0_P3_BASE + 0x16) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h3069 #define REG_COMBO_PHY0_P3_0B_L (REG_COMBO_PHY0_P3_BASE + 0x16) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h3067 #define REG_COMBO_PHY0_P3_0B_L (REG_COMBO_PHY0_P3_BASE + 0x16) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h3069 #define REG_COMBO_PHY0_P3_0B_L (REG_COMBO_PHY0_P3_BASE + 0x16) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h3069 #define REG_COMBO_PHY0_P3_0B_L (REG_COMBO_PHY0_P3_BASE + 0x16) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h3067 #define REG_COMBO_PHY0_P3_0B_L (REG_COMBO_PHY0_P3_BASE + 0x16) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h3068 #define REG_COMBO_PHY0_P3_0B_L (REG_COMBO_PHY0_P3_BASE + 0x16) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h3067 #define REG_COMBO_PHY0_P3_0B_L (REG_COMBO_PHY0_P3_BASE + 0x16) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h3067 #define REG_COMBO_PHY0_P3_0B_L (REG_COMBO_PHY0_P3_BASE + 0x16) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h3067 #define REG_COMBO_PHY0_P3_0B_L (REG_COMBO_PHY0_P3_BASE + 0x16) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h3067 #define REG_COMBO_PHY0_P3_0B_L (REG_COMBO_PHY0_P3_BASE + 0x16) macro