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Searched refs:REG_COMBO_PHY0_P2_7E_L (Results 1 – 24 of 24) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c3101 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3102 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3113 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3114 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3116 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3121 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3124 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3125 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3127 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3132 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c3138 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3139 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3150 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3151 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3153 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3158 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3161 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3162 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3164 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3169 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c3130 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3131 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3142 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3143 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3145 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3150 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3153 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3154 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3156 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3161 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c3138 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3139 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3150 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3151 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3153 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3158 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3161 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3162 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3164 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3169 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c3138 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3139 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3150 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3151 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3153 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3158 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3161 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3162 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3164 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3169 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c3130 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3131 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3142 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3143 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3145 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3150 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3153 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3154 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3156 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3161 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c3129 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3130 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3141 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3142 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3144 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3149 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3152 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3153 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3155 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3160 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c3132 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3133 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3144 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3145 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3147 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3152 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3155 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3156 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3158 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3163 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c3303 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3304 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3315 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3316 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3318 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3323 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3326 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3327 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3329 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3334 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c3132 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3133 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3144 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3145 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3147 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3152 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3155 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3156 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3158 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3163 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c3303 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3304 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3315 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3316 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3318 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3323 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3326 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3327 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3329 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3334 W2BYTEMSK(REG_COMBO_PHY0_P2_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h2781 #define REG_COMBO_PHY0_P2_7E_L (REG_COMBO_PHY0_P2_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h2783 #define REG_COMBO_PHY0_P2_7E_L (REG_COMBO_PHY0_P2_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h2781 #define REG_COMBO_PHY0_P2_7E_L (REG_COMBO_PHY0_P2_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h2783 #define REG_COMBO_PHY0_P2_7E_L (REG_COMBO_PHY0_P2_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h2781 #define REG_COMBO_PHY0_P2_7E_L (REG_COMBO_PHY0_P2_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h2783 #define REG_COMBO_PHY0_P2_7E_L (REG_COMBO_PHY0_P2_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h2783 #define REG_COMBO_PHY0_P2_7E_L (REG_COMBO_PHY0_P2_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h2781 #define REG_COMBO_PHY0_P2_7E_L (REG_COMBO_PHY0_P2_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h2782 #define REG_COMBO_PHY0_P2_7E_L (REG_COMBO_PHY0_P2_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h2781 #define REG_COMBO_PHY0_P2_7E_L (REG_COMBO_PHY0_P2_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h2781 #define REG_COMBO_PHY0_P2_7E_L (REG_COMBO_PHY0_P2_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h2781 #define REG_COMBO_PHY0_P2_7E_L (REG_COMBO_PHY0_P2_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h2781 #define REG_COMBO_PHY0_P2_7E_L (REG_COMBO_PHY0_P2_BASE + 0xFC) macro