| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_hdmi.c | 573 W2BYTEMSK(REG_COMBO_PHY0_P2_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
574 …W2BYTEMSK(REG_COMBO_PHY0_P2_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5102 if(R2BYTE(REG_COMBO_PHY0_P2_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_hdmi.c | 581 W2BYTEMSK(REG_COMBO_PHY0_P2_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
582 …W2BYTEMSK(REG_COMBO_PHY0_P2_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5202 if(R2BYTE(REG_COMBO_PHY0_P2_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 652 W2BYTEMSK(REG_COMBO_PHY0_P2_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
653 …W2BYTEMSK(REG_COMBO_PHY0_P2_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5240 if(R2BYTE(REG_COMBO_PHY0_P2_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_hdmi.c | 581 W2BYTEMSK(REG_COMBO_PHY0_P2_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
582 …W2BYTEMSK(REG_COMBO_PHY0_P2_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5202 if(R2BYTE(REG_COMBO_PHY0_P2_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 645 W2BYTEMSK(REG_COMBO_PHY0_P2_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
646 …W2BYTEMSK(REG_COMBO_PHY0_P2_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5213 if(R2BYTE(REG_COMBO_PHY0_P2_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 652 W2BYTEMSK(REG_COMBO_PHY0_P2_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
653 …W2BYTEMSK(REG_COMBO_PHY0_P2_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5240 if(R2BYTE(REG_COMBO_PHY0_P2_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_hdmi.c | 576 W2BYTEMSK(REG_COMBO_PHY0_P2_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
577 …W2BYTEMSK(REG_COMBO_PHY0_P2_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5805 if(R2BYTE(REG_COMBO_PHY0_P2_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_hdmi.c | 576 W2BYTEMSK(REG_COMBO_PHY0_P2_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
577 …W2BYTEMSK(REG_COMBO_PHY0_P2_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5808 if(R2BYTE(REG_COMBO_PHY0_P2_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 711 W2BYTEMSK(REG_COMBO_PHY0_P2_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
712 …W2BYTEMSK(REG_COMBO_PHY0_P2_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5511 if(R2BYTE(REG_COMBO_PHY0_P2_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_hdmi.c | 576 W2BYTEMSK(REG_COMBO_PHY0_P2_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
577 …W2BYTEMSK(REG_COMBO_PHY0_P2_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5811 if(R2BYTE(REG_COMBO_PHY0_P2_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 711 W2BYTEMSK(REG_COMBO_PHY0_P2_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
712 …W2BYTEMSK(REG_COMBO_PHY0_P2_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5511 if(R2BYTE(REG_COMBO_PHY0_P2_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_hdmi.c | 2743 if(R2BYTE(REG_COMBO_PHY0_P2_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_hdmi.c | 3480 if(R2BYTE(REG_COMBO_PHY0_P2_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 2629 #define REG_COMBO_PHY0_P2_32_L (REG_COMBO_PHY0_P2_BASE + 0x64) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 2631 #define REG_COMBO_PHY0_P2_32_L (REG_COMBO_PHY0_P2_BASE + 0x64) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_hdmi.h | 2629 #define REG_COMBO_PHY0_P2_32_L (REG_COMBO_PHY0_P2_BASE + 0x64) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_hdmi.h | 2631 #define REG_COMBO_PHY0_P2_32_L (REG_COMBO_PHY0_P2_BASE + 0x64) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_hdmi.h | 2629 #define REG_COMBO_PHY0_P2_32_L (REG_COMBO_PHY0_P2_BASE + 0x64) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_hdmi.h | 2631 #define REG_COMBO_PHY0_P2_32_L (REG_COMBO_PHY0_P2_BASE + 0x64) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_hdmi.h | 2631 #define REG_COMBO_PHY0_P2_32_L (REG_COMBO_PHY0_P2_BASE + 0x64) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_hdmi.h | 2629 #define REG_COMBO_PHY0_P2_32_L (REG_COMBO_PHY0_P2_BASE + 0x64) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_hdmi.h | 2630 #define REG_COMBO_PHY0_P2_32_L (REG_COMBO_PHY0_P2_BASE + 0x64) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_hdmi.h | 2629 #define REG_COMBO_PHY0_P2_32_L (REG_COMBO_PHY0_P2_BASE + 0x64) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_hdmi.h | 2629 #define REG_COMBO_PHY0_P2_32_L (REG_COMBO_PHY0_P2_BASE + 0x64) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_hdmi.h | 2629 #define REG_COMBO_PHY0_P2_32_L (REG_COMBO_PHY0_P2_BASE + 0x64) macro
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