| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_hdmi.c | 568 W2BYTEMSK(REG_COMBO_PHY0_P1_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
569 …W2BYTEMSK(REG_COMBO_PHY0_P1_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5061 if(R2BYTE(REG_COMBO_PHY0_P1_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_hdmi.c | 576 W2BYTEMSK(REG_COMBO_PHY0_P1_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
577 …W2BYTEMSK(REG_COMBO_PHY0_P1_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5161 if(R2BYTE(REG_COMBO_PHY0_P1_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 647 W2BYTEMSK(REG_COMBO_PHY0_P1_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
648 …W2BYTEMSK(REG_COMBO_PHY0_P1_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5199 if(R2BYTE(REG_COMBO_PHY0_P1_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_hdmi.c | 576 W2BYTEMSK(REG_COMBO_PHY0_P1_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
577 …W2BYTEMSK(REG_COMBO_PHY0_P1_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5161 if(R2BYTE(REG_COMBO_PHY0_P1_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 640 W2BYTEMSK(REG_COMBO_PHY0_P1_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
641 …W2BYTEMSK(REG_COMBO_PHY0_P1_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5172 if(R2BYTE(REG_COMBO_PHY0_P1_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 647 W2BYTEMSK(REG_COMBO_PHY0_P1_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
648 …W2BYTEMSK(REG_COMBO_PHY0_P1_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5199 if(R2BYTE(REG_COMBO_PHY0_P1_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_hdmi.c | 571 W2BYTEMSK(REG_COMBO_PHY0_P1_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
572 …W2BYTEMSK(REG_COMBO_PHY0_P1_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5764 if(R2BYTE(REG_COMBO_PHY0_P1_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_hdmi.c | 571 W2BYTEMSK(REG_COMBO_PHY0_P1_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
572 …W2BYTEMSK(REG_COMBO_PHY0_P1_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5767 if(R2BYTE(REG_COMBO_PHY0_P1_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 706 W2BYTEMSK(REG_COMBO_PHY0_P1_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
707 …W2BYTEMSK(REG_COMBO_PHY0_P1_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5470 if(R2BYTE(REG_COMBO_PHY0_P1_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_hdmi.c | 571 W2BYTEMSK(REG_COMBO_PHY0_P1_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
572 …W2BYTEMSK(REG_COMBO_PHY0_P1_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5770 if(R2BYTE(REG_COMBO_PHY0_P1_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 706 W2BYTEMSK(REG_COMBO_PHY0_P1_32_L, 0, BIT(12)| BIT(8)| BIT(4)| BIT(0)); in _Hal_tmds_ResetClockDetect()
707 …W2BYTEMSK(REG_COMBO_PHY0_P1_32_L, BIT(12)| BIT(8)| BIT(4)| BIT(0), BIT(12)| BIT(8)| BIT(4)| BIT(0)… in _Hal_tmds_ResetClockDetect()
5470 if(R2BYTE(REG_COMBO_PHY0_P1_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_hdmi.c | 2702 if(R2BYTE(REG_COMBO_PHY0_P1_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_hdmi.c | 3439 if(R2BYTE(REG_COMBO_PHY0_P1_32_L) & BIT(3)& BIT(7)& BIT(11)& BIT(15)) // clk stable in Hal_DVI_HF_adjust()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 2113 #define REG_COMBO_PHY0_P1_32_L (REG_COMBO_PHY0_P1_BASE + 0x64) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 2115 #define REG_COMBO_PHY0_P1_32_L (REG_COMBO_PHY0_P1_BASE + 0x64) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_hdmi.h | 2113 #define REG_COMBO_PHY0_P1_32_L (REG_COMBO_PHY0_P1_BASE + 0x64) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_hdmi.h | 2115 #define REG_COMBO_PHY0_P1_32_L (REG_COMBO_PHY0_P1_BASE + 0x64) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_hdmi.h | 2113 #define REG_COMBO_PHY0_P1_32_L (REG_COMBO_PHY0_P1_BASE + 0x64) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_hdmi.h | 2115 #define REG_COMBO_PHY0_P1_32_L (REG_COMBO_PHY0_P1_BASE + 0x64) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_hdmi.h | 2115 #define REG_COMBO_PHY0_P1_32_L (REG_COMBO_PHY0_P1_BASE + 0x64) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_hdmi.h | 2113 #define REG_COMBO_PHY0_P1_32_L (REG_COMBO_PHY0_P1_BASE + 0x64) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_hdmi.h | 2114 #define REG_COMBO_PHY0_P1_32_L (REG_COMBO_PHY0_P1_BASE + 0x64) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_hdmi.h | 2113 #define REG_COMBO_PHY0_P1_32_L (REG_COMBO_PHY0_P1_BASE + 0x64) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_hdmi.h | 2113 #define REG_COMBO_PHY0_P1_32_L (REG_COMBO_PHY0_P1_BASE + 0x64) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_hdmi.h | 2113 #define REG_COMBO_PHY0_P1_32_L (REG_COMBO_PHY0_P1_BASE + 0x64) macro
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