| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_hdmi.c | 377 W2BYTEMSK(REG_COMBO_PHY0_P0_5A_L, BIT(2), BIT(2)); // [2]: disable reg_atop_en_clko_tmds2x in _Hal_tmds_HDMI20PHYSetting()
1906 W2BYTE(REG_COMBO_PHY0_P0_5A_L, 0x0004);// [2]: enable reg_atop_en_clko_tmds2x in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_hdmi.c | 474 …W2BYTEMSK(REG_COMBO_PHY0_P0_5A_L, bHDMI20Flag? 0: BIT(2), BIT(2)); // [2]: disable reg_atop_en_clk… in _Hal_tmds_HDMI20PHYSetting()
2641 W2BYTE(REG_COMBO_PHY0_P0_5A_L, 0x0004);// [2]: enable reg_atop_en_clko_tmds2x in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_hdmi.c | 706 …W2BYTEMSK(REG_COMBO_PHY0_P0_5A_L, bHDMI20Flag? 0: BIT(2), BIT(2)); // [2]: disable reg_atop_en_clk… in _Hal_tmds_HDMI20PHYSetting()
4100 … W2BYTE(REG_COMBO_PHY0_P0_5A_L + u16bank_offset, 0x0004);// [2]: enable reg_atop_en_clko_tmds2x in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_hdmi.c | 717 …W2BYTEMSK(REG_COMBO_PHY0_P0_5A_L, bHDMI20Flag? 0: BIT(2), BIT(2)); // [2]: disable reg_atop_en_clk… in _Hal_tmds_HDMI20PHYSetting()
4209 … W2BYTE(REG_COMBO_PHY0_P0_5A_L + u16bank_offset, 0x0004);// [2]: enable reg_atop_en_clko_tmds2x in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 788 …W2BYTEMSK(REG_COMBO_PHY0_P0_5A_L, bHDMI20Flag? 0: BIT(2), BIT(2)); // [2]: disable reg_atop_en_clk… in _Hal_tmds_HDMI20PHYSetting()
4214 … W2BYTE(REG_COMBO_PHY0_P0_5A_L + u16bank_offset, 0x0004);// [2]: enable reg_atop_en_clko_tmds2x in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_hdmi.c | 717 …W2BYTEMSK(REG_COMBO_PHY0_P0_5A_L, bHDMI20Flag? 0: BIT(2), BIT(2)); // [2]: disable reg_atop_en_clk… in _Hal_tmds_HDMI20PHYSetting()
4209 … W2BYTE(REG_COMBO_PHY0_P0_5A_L + u16bank_offset, 0x0004);// [2]: enable reg_atop_en_clko_tmds2x in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 778 …W2BYTEMSK(REG_COMBO_PHY0_P0_5A_L, bHDMI20Flag? 0: BIT(2), BIT(2)); // [2]: disable reg_atop_en_clk… in _Hal_tmds_HDMI20PHYSetting()
4145 … W2BYTE(REG_COMBO_PHY0_P0_5A_L + u16bank_offset, 0x0004);// [2]: enable reg_atop_en_clko_tmds2x in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 788 …W2BYTEMSK(REG_COMBO_PHY0_P0_5A_L, bHDMI20Flag? 0: BIT(2), BIT(2)); // [2]: disable reg_atop_en_clk… in _Hal_tmds_HDMI20PHYSetting()
4214 … W2BYTE(REG_COMBO_PHY0_P0_5A_L + u16bank_offset, 0x0004);// [2]: enable reg_atop_en_clko_tmds2x in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_hdmi.c | 709 …W2BYTEMSK(REG_COMBO_PHY0_P0_5A_L, bHDMI20Flag? 0: BIT(2), BIT(2)); // [2]: disable reg_atop_en_clk… in _Hal_tmds_HDMI20PHYSetting()
4776 … W2BYTE(REG_COMBO_PHY0_P0_5A_L + u16bank_offset, 0x0004);// [2]: enable reg_atop_en_clko_tmds2x in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_hdmi.c | 709 …W2BYTEMSK(REG_COMBO_PHY0_P0_5A_L, bHDMI20Flag? 0: BIT(2), BIT(2)); // [2]: disable reg_atop_en_clk… in _Hal_tmds_HDMI20PHYSetting()
4779 … W2BYTE(REG_COMBO_PHY0_P0_5A_L + u16bank_offset, 0x0004);// [2]: enable reg_atop_en_clko_tmds2x in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 844 …W2BYTEMSK(REG_COMBO_PHY0_P0_5A_L, bHDMI20Flag? 0: BIT(2), BIT(2)); // [2]: disable reg_atop_en_clk… in _Hal_tmds_HDMI20PHYSetting()
4336 … W2BYTE(REG_COMBO_PHY0_P0_5A_L + u16bank_offset, 0x0004);// [2]: enable reg_atop_en_clko_tmds2x in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_hdmi.c | 709 …W2BYTEMSK(REG_COMBO_PHY0_P0_5A_L, bHDMI20Flag? 0: BIT(2), BIT(2)); // [2]: disable reg_atop_en_clk… in _Hal_tmds_HDMI20PHYSetting()
4782 … W2BYTE(REG_COMBO_PHY0_P0_5A_L + u16bank_offset, 0x0004);// [2]: enable reg_atop_en_clko_tmds2x in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 844 …W2BYTEMSK(REG_COMBO_PHY0_P0_5A_L, bHDMI20Flag? 0: BIT(2), BIT(2)); // [2]: disable reg_atop_en_clk… in _Hal_tmds_HDMI20PHYSetting()
4336 … W2BYTE(REG_COMBO_PHY0_P0_5A_L + u16bank_offset, 0x0004);// [2]: enable reg_atop_en_clko_tmds2x in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 1677 #define REG_COMBO_PHY0_P0_5A_L (REG_COMBO_PHY0_P0_BASE + 0xB4) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 1679 #define REG_COMBO_PHY0_P0_5A_L (REG_COMBO_PHY0_P0_BASE + 0xB4) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_hdmi.h | 1677 #define REG_COMBO_PHY0_P0_5A_L (REG_COMBO_PHY0_P0_BASE + 0xB4) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_hdmi.h | 1679 #define REG_COMBO_PHY0_P0_5A_L (REG_COMBO_PHY0_P0_BASE + 0xB4) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_hdmi.h | 1677 #define REG_COMBO_PHY0_P0_5A_L (REG_COMBO_PHY0_P0_BASE + 0xB4) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_hdmi.h | 1679 #define REG_COMBO_PHY0_P0_5A_L (REG_COMBO_PHY0_P0_BASE + 0xB4) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_hdmi.h | 1679 #define REG_COMBO_PHY0_P0_5A_L (REG_COMBO_PHY0_P0_BASE + 0xB4) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_hdmi.h | 1677 #define REG_COMBO_PHY0_P0_5A_L (REG_COMBO_PHY0_P0_BASE + 0xB4) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_hdmi.h | 1678 #define REG_COMBO_PHY0_P0_5A_L (REG_COMBO_PHY0_P0_BASE + 0xB4) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_hdmi.h | 1677 #define REG_COMBO_PHY0_P0_5A_L (REG_COMBO_PHY0_P0_BASE + 0xB4) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_hdmi.h | 1677 #define REG_COMBO_PHY0_P0_5A_L (REG_COMBO_PHY0_P0_BASE + 0xB4) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_hdmi.h | 1677 #define REG_COMBO_PHY0_P0_5A_L (REG_COMBO_PHY0_P0_BASE + 0xB4) macro
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