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Searched refs:REG_COMBO_PHY0_P0_4D_L (Results 1 – 25 of 26) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_hdmi.c1932 W2BYTE(REG_COMBO_PHY0_P0_4D_L, 0x038B); //[15:0]: reg_mhlpp_clk_thr2 (85Mhz) in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_hdmi.c2667 W2BYTE(REG_COMBO_PHY0_P0_4D_L, 0x038B); //[15:0]: reg_mhlpp_clk_thr2 (85Mhz) in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c4128 … W2BYTE(REG_COMBO_PHY0_P0_4D_L + u16bank_offset, 0x038B); //[15:0]: reg_mhlpp_clk_thr2 (85Mhz) in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c4237 … W2BYTE(REG_COMBO_PHY0_P0_4D_L + u16bank_offset, 0x038B); //[15:0]: reg_mhlpp_clk_thr2 (85Mhz) in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c4241 … W2BYTE(REG_COMBO_PHY0_P0_4D_L + u16bank_offset, 0x038B); //[15:0]: reg_mhlpp_clk_thr2 (85Mhz) in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c4237 … W2BYTE(REG_COMBO_PHY0_P0_4D_L + u16bank_offset, 0x038B); //[15:0]: reg_mhlpp_clk_thr2 (85Mhz) in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c4179 … W2BYTE(REG_COMBO_PHY0_P0_4D_L + u16bank_offset, 0x038B); //[15:0]: reg_mhlpp_clk_thr2 (85Mhz) in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c4241 … W2BYTE(REG_COMBO_PHY0_P0_4D_L + u16bank_offset, 0x038B); //[15:0]: reg_mhlpp_clk_thr2 (85Mhz) in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c4805 … W2BYTE(REG_COMBO_PHY0_P0_4D_L + u16bank_offset, 0x038B); //[15:0]: reg_mhlpp_clk_thr2 (85Mhz) in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c4808 … W2BYTE(REG_COMBO_PHY0_P0_4D_L + u16bank_offset, 0x038B); //[15:0]: reg_mhlpp_clk_thr2 (85Mhz) in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c4363 … W2BYTE(REG_COMBO_PHY0_P0_4D_L + u16bank_offset, 0x038B); //[15:0]: reg_mhlpp_clk_thr2 (85Mhz) in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c4811 … W2BYTE(REG_COMBO_PHY0_P0_4D_L + u16bank_offset, 0x038B); //[15:0]: reg_mhlpp_clk_thr2 (85Mhz) in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c4363 … W2BYTE(REG_COMBO_PHY0_P0_4D_L + u16bank_offset, 0x038B); //[15:0]: reg_mhlpp_clk_thr2 (85Mhz) in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h1651 #define REG_COMBO_PHY0_P0_4D_L (REG_COMBO_PHY0_P0_BASE + 0x9A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h1653 #define REG_COMBO_PHY0_P0_4D_L (REG_COMBO_PHY0_P0_BASE + 0x9A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h1651 #define REG_COMBO_PHY0_P0_4D_L (REG_COMBO_PHY0_P0_BASE + 0x9A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h1653 #define REG_COMBO_PHY0_P0_4D_L (REG_COMBO_PHY0_P0_BASE + 0x9A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h1651 #define REG_COMBO_PHY0_P0_4D_L (REG_COMBO_PHY0_P0_BASE + 0x9A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h1653 #define REG_COMBO_PHY0_P0_4D_L (REG_COMBO_PHY0_P0_BASE + 0x9A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h1653 #define REG_COMBO_PHY0_P0_4D_L (REG_COMBO_PHY0_P0_BASE + 0x9A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h1651 #define REG_COMBO_PHY0_P0_4D_L (REG_COMBO_PHY0_P0_BASE + 0x9A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h1652 #define REG_COMBO_PHY0_P0_4D_L (REG_COMBO_PHY0_P0_BASE + 0x9A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h1651 #define REG_COMBO_PHY0_P0_4D_L (REG_COMBO_PHY0_P0_BASE + 0x9A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h1651 #define REG_COMBO_PHY0_P0_4D_L (REG_COMBO_PHY0_P0_BASE + 0x9A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h1651 #define REG_COMBO_PHY0_P0_4D_L (REG_COMBO_PHY0_P0_BASE + 0x9A) macro

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