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Searched refs:REG_COMBO_PHY0_P0_48_L (Results 1 – 25 of 26) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_hdmi.c1923 …W2BYTE(REG_COMBO_PHY0_P0_48_L, 0x0702);// [15:8]: reg_mainlink_crlose_thr; [7:0]: reg_mainlink_crl… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_hdmi.c2658 …W2BYTE(REG_COMBO_PHY0_P0_48_L, 0x0702);// [15:8]: reg_mainlink_crlose_thr; [7:0]: reg_mainlink_crl… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c4117 …W2BYTE(REG_COMBO_PHY0_P0_48_L + u16bank_offset, 0x0702);// [15:8]: reg_mainlink_crlose_thr; [7:0]:… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c4226 …W2BYTE(REG_COMBO_PHY0_P0_48_L + u16bank_offset, 0x0702);// [15:8]: reg_mainlink_crlose_thr; [7:0]:… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c4231 …W2BYTE(REG_COMBO_PHY0_P0_48_L + u16bank_offset, 0x0702);// [15:8]: reg_mainlink_crlose_thr; [7:0]:… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c4226 …W2BYTE(REG_COMBO_PHY0_P0_48_L + u16bank_offset, 0x0702);// [15:8]: reg_mainlink_crlose_thr; [7:0]:… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c4162 …W2BYTE(REG_COMBO_PHY0_P0_48_L + u16bank_offset, 0x0702);// [15:8]: reg_mainlink_crlose_thr; [7:0]:… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c4231 …W2BYTE(REG_COMBO_PHY0_P0_48_L + u16bank_offset, 0x0702);// [15:8]: reg_mainlink_crlose_thr; [7:0]:… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c4794 …W2BYTE(REG_COMBO_PHY0_P0_48_L + u16bank_offset, 0x0702);// [15:8]: reg_mainlink_crlose_thr; [7:0]:… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c4797 …W2BYTE(REG_COMBO_PHY0_P0_48_L + u16bank_offset, 0x0702);// [15:8]: reg_mainlink_crlose_thr; [7:0]:… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c4353 …W2BYTE(REG_COMBO_PHY0_P0_48_L + u16bank_offset, 0x0702);// [15:8]: reg_mainlink_crlose_thr; [7:0]:… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c4800 …W2BYTE(REG_COMBO_PHY0_P0_48_L + u16bank_offset, 0x0702);// [15:8]: reg_mainlink_crlose_thr; [7:0]:… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c4353 …W2BYTE(REG_COMBO_PHY0_P0_48_L + u16bank_offset, 0x0702);// [15:8]: reg_mainlink_crlose_thr; [7:0]:… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h1641 #define REG_COMBO_PHY0_P0_48_L (REG_COMBO_PHY0_P0_BASE + 0x90) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h1643 #define REG_COMBO_PHY0_P0_48_L (REG_COMBO_PHY0_P0_BASE + 0x90) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h1641 #define REG_COMBO_PHY0_P0_48_L (REG_COMBO_PHY0_P0_BASE + 0x90) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h1643 #define REG_COMBO_PHY0_P0_48_L (REG_COMBO_PHY0_P0_BASE + 0x90) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h1641 #define REG_COMBO_PHY0_P0_48_L (REG_COMBO_PHY0_P0_BASE + 0x90) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h1643 #define REG_COMBO_PHY0_P0_48_L (REG_COMBO_PHY0_P0_BASE + 0x90) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h1643 #define REG_COMBO_PHY0_P0_48_L (REG_COMBO_PHY0_P0_BASE + 0x90) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h1641 #define REG_COMBO_PHY0_P0_48_L (REG_COMBO_PHY0_P0_BASE + 0x90) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h1642 #define REG_COMBO_PHY0_P0_48_L (REG_COMBO_PHY0_P0_BASE + 0x90) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h1641 #define REG_COMBO_PHY0_P0_48_L (REG_COMBO_PHY0_P0_BASE + 0x90) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h1641 #define REG_COMBO_PHY0_P0_48_L (REG_COMBO_PHY0_P0_BASE + 0x90) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h1641 #define REG_COMBO_PHY0_P0_48_L (REG_COMBO_PHY0_P0_BASE + 0x90) macro

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