| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_hdmi.c | 1920 W2BYTE(REG_COMBO_PHY0_P0_35_L, 0x0480); // [10]: reg_hdmi2_acdr_mode = 1 in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_hdmi.c | 2655 W2BYTE(REG_COMBO_PHY0_P0_35_L, 0x0480); // [10]: reg_hdmi2_acdr_mode = 1 in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_hdmi.c | 4114 W2BYTE(REG_COMBO_PHY0_P0_35_L + u16bank_offset, 0x0480); // [10]: reg_hdmi2_acdr_mode = 1 in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_hdmi.c | 4223 W2BYTE(REG_COMBO_PHY0_P0_35_L + u16bank_offset, 0x0480); // [10]: reg_hdmi2_acdr_mode = 1 in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 4228 W2BYTE(REG_COMBO_PHY0_P0_35_L + u16bank_offset, 0x0480); // [10]: reg_hdmi2_acdr_mode = 1 in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_hdmi.c | 4223 W2BYTE(REG_COMBO_PHY0_P0_35_L + u16bank_offset, 0x0480); // [10]: reg_hdmi2_acdr_mode = 1 in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 4159 W2BYTE(REG_COMBO_PHY0_P0_35_L + u16bank_offset, 0x0480); // [10]: reg_hdmi2_acdr_mode = 1 in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 4228 W2BYTE(REG_COMBO_PHY0_P0_35_L + u16bank_offset, 0x0480); // [10]: reg_hdmi2_acdr_mode = 1 in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_hdmi.c | 4790 W2BYTE(REG_COMBO_PHY0_P0_35_L + u16bank_offset, 0x0080); // [10]: reg_hdmi2_acdr_mode = 1 in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_hdmi.c | 4793 W2BYTE(REG_COMBO_PHY0_P0_35_L + u16bank_offset, 0x0080); // [10]: reg_hdmi2_acdr_mode = 1 in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 4350 W2BYTE(REG_COMBO_PHY0_P0_35_L + u16bank_offset, 0x0480); // [10]: reg_hdmi2_acdr_mode = 1 in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_hdmi.c | 4796 W2BYTE(REG_COMBO_PHY0_P0_35_L + u16bank_offset, 0x0080); // [10]: reg_hdmi2_acdr_mode = 1 in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 4350 W2BYTE(REG_COMBO_PHY0_P0_35_L + u16bank_offset, 0x0480); // [10]: reg_hdmi2_acdr_mode = 1 in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 1603 #define REG_COMBO_PHY0_P0_35_L (REG_COMBO_PHY0_P0_BASE + 0x6A) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 1605 #define REG_COMBO_PHY0_P0_35_L (REG_COMBO_PHY0_P0_BASE + 0x6A) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_hdmi.h | 1603 #define REG_COMBO_PHY0_P0_35_L (REG_COMBO_PHY0_P0_BASE + 0x6A) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_hdmi.h | 1605 #define REG_COMBO_PHY0_P0_35_L (REG_COMBO_PHY0_P0_BASE + 0x6A) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_hdmi.h | 1603 #define REG_COMBO_PHY0_P0_35_L (REG_COMBO_PHY0_P0_BASE + 0x6A) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_hdmi.h | 1605 #define REG_COMBO_PHY0_P0_35_L (REG_COMBO_PHY0_P0_BASE + 0x6A) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_hdmi.h | 1605 #define REG_COMBO_PHY0_P0_35_L (REG_COMBO_PHY0_P0_BASE + 0x6A) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_hdmi.h | 1603 #define REG_COMBO_PHY0_P0_35_L (REG_COMBO_PHY0_P0_BASE + 0x6A) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_hdmi.h | 1604 #define REG_COMBO_PHY0_P0_35_L (REG_COMBO_PHY0_P0_BASE + 0x6A) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_hdmi.h | 1603 #define REG_COMBO_PHY0_P0_35_L (REG_COMBO_PHY0_P0_BASE + 0x6A) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_hdmi.h | 1603 #define REG_COMBO_PHY0_P0_35_L (REG_COMBO_PHY0_P0_BASE + 0x6A) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_hdmi.h | 1603 #define REG_COMBO_PHY0_P0_35_L (REG_COMBO_PHY0_P0_BASE + 0x6A) macro
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