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Searched refs:REG_COMBO_PHY0_P0_25_L (Results 1 – 25 of 31) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_hdmi.c712 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, BIT(2), BIT(2)); in _Hal_tmds_AutoEQFunctionEnable()
718 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, 0, BIT(2)); in _Hal_tmds_AutoEQFunctionEnable()
1937 W2BYTE(REG_COMBO_PHY0_P0_25_L, 0x0AC8); in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_hdmi.c914 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, BIT(2), BIT(2)); in _Hal_tmds_AutoEQFunctionEnable()
920 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, 0, BIT(2)); in _Hal_tmds_AutoEQFunctionEnable()
2672 W2BYTE(REG_COMBO_PHY0_P0_25_L, 0x0AC8); in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c1794 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, BIT(2), BIT(2)); in _Hal_tmds_AutoEQFunctionEnable()
1800 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, 0, BIT(2)); in _Hal_tmds_AutoEQFunctionEnable()
4133 W2BYTE(REG_COMBO_PHY0_P0_25_L + u16bank_offset, 0x0AC8); in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c1824 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, BIT(2), BIT(2)); in _Hal_tmds_AutoEQFunctionEnable()
1830 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, 0, BIT(2)); in _Hal_tmds_AutoEQFunctionEnable()
4242 W2BYTE(REG_COMBO_PHY0_P0_25_L + u16bank_offset, 0x0AC8); in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c1863 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, BIT(2), BIT(2)); in _Hal_tmds_AutoEQFunctionEnable()
1869 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, 0, BIT(2)); in _Hal_tmds_AutoEQFunctionEnable()
4246 W2BYTE(REG_COMBO_PHY0_P0_25_L + u16bank_offset, 0x0AC8); in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c1824 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, BIT(2), BIT(2)); in _Hal_tmds_AutoEQFunctionEnable()
1830 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, 0, BIT(2)); in _Hal_tmds_AutoEQFunctionEnable()
4242 W2BYTE(REG_COMBO_PHY0_P0_25_L + u16bank_offset, 0x0AC8); in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c1870 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, BIT(2), BIT(2)); in _Hal_tmds_AutoEQFunctionEnable()
1876 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, 0, BIT(2)); in _Hal_tmds_AutoEQFunctionEnable()
4184 W2BYTE(REG_COMBO_PHY0_P0_25_L + u16bank_offset, 0x0AC8); in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c1863 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, BIT(2), BIT(2)); in _Hal_tmds_AutoEQFunctionEnable()
1869 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, 0, BIT(2)); in _Hal_tmds_AutoEQFunctionEnable()
4246 W2BYTE(REG_COMBO_PHY0_P0_25_L + u16bank_offset, 0x0AC8); in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c1797 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, BIT(2), BIT(2)); in _Hal_tmds_AutoEQFunctionEnable()
1804 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, 0, BIT(2)); in _Hal_tmds_AutoEQFunctionEnable()
4810 W2BYTE(REG_COMBO_PHY0_P0_25_L + u16bank_offset, 0x0AC8); in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c1797 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, BIT(2), BIT(2)); in _Hal_tmds_AutoEQFunctionEnable()
1804 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, 0, BIT(2)); in _Hal_tmds_AutoEQFunctionEnable()
4813 W2BYTE(REG_COMBO_PHY0_P0_25_L + u16bank_offset, 0x0AC8); in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c1963 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, BIT(2), BIT(2)); in _Hal_tmds_AutoEQFunctionEnable()
1969 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, 0, BIT(2)); in _Hal_tmds_AutoEQFunctionEnable()
4368 W2BYTE(REG_COMBO_PHY0_P0_25_L + u16bank_offset, 0x0AC8); in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c1797 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, BIT(2), BIT(2)); in _Hal_tmds_AutoEQFunctionEnable()
1804 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, 0, BIT(2)); in _Hal_tmds_AutoEQFunctionEnable()
4816 W2BYTE(REG_COMBO_PHY0_P0_25_L + u16bank_offset, 0x0AC8); in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c1963 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, BIT(2), BIT(2)); in _Hal_tmds_AutoEQFunctionEnable()
1969 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, 0, BIT(2)); in _Hal_tmds_AutoEQFunctionEnable()
4368 W2BYTE(REG_COMBO_PHY0_P0_25_L + u16bank_offset, 0x0AC8); in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/
H A DhalMHL.c2513 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, BIT(2), BIT(2)); in _mhal_mhl_MHL30AutoEQEnable()
2519 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, 0, BIT(2)); in _mhal_mhl_MHL30AutoEQEnable()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/
H A DhalMHL.c2513 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, BIT(2), BIT(2)); in _mhal_mhl_MHL30AutoEQEnable()
2519 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, 0, BIT(2)); in _mhal_mhl_MHL30AutoEQEnable()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/
H A DhalMHL.c2513 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, BIT(2), BIT(2)); in _mhal_mhl_MHL30AutoEQEnable()
2519 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, 0, BIT(2)); in _mhal_mhl_MHL30AutoEQEnable()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/
H A DhalMHL.c2513 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, BIT(2), BIT(2)); in _mhal_mhl_MHL30AutoEQEnable()
2519 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, 0, BIT(2)); in _mhal_mhl_MHL30AutoEQEnable()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/
H A DhalMHL.c2513 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, BIT(2), BIT(2)); in _mhal_mhl_MHL30AutoEQEnable()
2519 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, 0, BIT(2)); in _mhal_mhl_MHL30AutoEQEnable()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h1571 #define REG_COMBO_PHY0_P0_25_L (REG_COMBO_PHY0_P0_BASE + 0x4A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h1573 #define REG_COMBO_PHY0_P0_25_L (REG_COMBO_PHY0_P0_BASE + 0x4A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h1571 #define REG_COMBO_PHY0_P0_25_L (REG_COMBO_PHY0_P0_BASE + 0x4A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h1573 #define REG_COMBO_PHY0_P0_25_L (REG_COMBO_PHY0_P0_BASE + 0x4A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h1571 #define REG_COMBO_PHY0_P0_25_L (REG_COMBO_PHY0_P0_BASE + 0x4A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h1573 #define REG_COMBO_PHY0_P0_25_L (REG_COMBO_PHY0_P0_BASE + 0x4A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h1573 #define REG_COMBO_PHY0_P0_25_L (REG_COMBO_PHY0_P0_BASE + 0x4A) macro

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