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Searched refs:REG_COMBO_PHY0_P0_1D_L (Results 1 – 25 of 26) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_hdmi.c1947 …W2BYTE(REG_COMBO_PHY0_P0_1D_L, 0x0100); // dvi phase update threshold for accumulator, [7]enable, … in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_hdmi.c2682 …W2BYTE(REG_COMBO_PHY0_P0_1D_L, 0x0100); // dvi phase update threshold for accumulator, [7]enable, … in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c4143 …W2BYTE(REG_COMBO_PHY0_P0_1D_L + u16bank_offset, 0x0100); // dvi phase update threshold for accumul… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c4252 …W2BYTE(REG_COMBO_PHY0_P0_1D_L + u16bank_offset, 0x0100); // dvi phase update threshold for accumul… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c4256 …W2BYTE(REG_COMBO_PHY0_P0_1D_L + u16bank_offset, 0x0100); // dvi phase update threshold for accumul… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c4252 …W2BYTE(REG_COMBO_PHY0_P0_1D_L + u16bank_offset, 0x0100); // dvi phase update threshold for accumul… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c4194 …W2BYTE(REG_COMBO_PHY0_P0_1D_L + u16bank_offset, 0x0100); // dvi phase update threshold for accumul… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c4256 …W2BYTE(REG_COMBO_PHY0_P0_1D_L + u16bank_offset, 0x0100); // dvi phase update threshold for accumul… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c4820 …W2BYTE(REG_COMBO_PHY0_P0_1D_L + u16bank_offset, 0x0100); // dvi phase update threshold for accumul… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c4823 …W2BYTE(REG_COMBO_PHY0_P0_1D_L + u16bank_offset, 0x0100); // dvi phase update threshold for accumul… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c4378 …W2BYTE(REG_COMBO_PHY0_P0_1D_L + u16bank_offset, 0x0100); // dvi phase update threshold for accumul… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c4826 …W2BYTE(REG_COMBO_PHY0_P0_1D_L + u16bank_offset, 0x0100); // dvi phase update threshold for accumul… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c4378 …W2BYTE(REG_COMBO_PHY0_P0_1D_L + u16bank_offset, 0x0100); // dvi phase update threshold for accumul… in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h1555 #define REG_COMBO_PHY0_P0_1D_L (REG_COMBO_PHY0_P0_BASE + 0x3A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h1557 #define REG_COMBO_PHY0_P0_1D_L (REG_COMBO_PHY0_P0_BASE + 0x3A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h1555 #define REG_COMBO_PHY0_P0_1D_L (REG_COMBO_PHY0_P0_BASE + 0x3A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h1557 #define REG_COMBO_PHY0_P0_1D_L (REG_COMBO_PHY0_P0_BASE + 0x3A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h1555 #define REG_COMBO_PHY0_P0_1D_L (REG_COMBO_PHY0_P0_BASE + 0x3A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h1557 #define REG_COMBO_PHY0_P0_1D_L (REG_COMBO_PHY0_P0_BASE + 0x3A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h1557 #define REG_COMBO_PHY0_P0_1D_L (REG_COMBO_PHY0_P0_BASE + 0x3A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h1555 #define REG_COMBO_PHY0_P0_1D_L (REG_COMBO_PHY0_P0_BASE + 0x3A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h1556 #define REG_COMBO_PHY0_P0_1D_L (REG_COMBO_PHY0_P0_BASE + 0x3A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h1555 #define REG_COMBO_PHY0_P0_1D_L (REG_COMBO_PHY0_P0_BASE + 0x3A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h1555 #define REG_COMBO_PHY0_P0_1D_L (REG_COMBO_PHY0_P0_BASE + 0x3A) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h1555 #define REG_COMBO_PHY0_P0_1D_L (REG_COMBO_PHY0_P0_BASE + 0x3A) macro

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