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Searched refs:REG_COMBO_GP_TOP_07_L (Results 1 – 25 of 45) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_mux.c317 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
340 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
363 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
386 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
409 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c1884 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_mux.c317 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
351 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
385 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
419 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
452 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c3988 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_mux.c317 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
341 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
365 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
389 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
413 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c2619 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_mux.c317 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
351 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
385 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
419 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
452 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_mux.c317 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
351 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
385 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
419 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
452 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_mux.c317 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
351 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
385 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
419 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
452 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_mux.c317 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
351 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
385 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
419 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
452 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_mux.c317 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
351 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
385 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
419 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
452 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_mux.c317 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
351 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
385 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
419 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
452 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdcp/
H A DregHDCP.h385 #define REG_COMBO_GP_TOP_07_L 0x07U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/hdcp/
H A DregHDCP.h385 #define REG_COMBO_GP_TOP_07_L 0x07U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdcp/
H A DregHDCP.h385 #define REG_COMBO_GP_TOP_07_L 0x07U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/hdcp/
H A DregHDCP.h385 #define REG_COMBO_GP_TOP_07_L 0x07U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdcp/
H A DregHDCP.h385 #define REG_COMBO_GP_TOP_07_L 0x07U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/hdcp/
H A DregHDCP.h385 #define REG_COMBO_GP_TOP_07_L 0x07U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/hdcp/
H A DregHDCP.h385 #define REG_COMBO_GP_TOP_07_L 0x07U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdcp/
H A DregHDCP.h385 #define REG_COMBO_GP_TOP_07_L 0x07U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/hdcp/
H A DregHDCP.h385 #define REG_COMBO_GP_TOP_07_L 0x07U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdcp/
H A DregHDCP.h385 #define REG_COMBO_GP_TOP_07_L 0x07U macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c4093 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_HDMI_init()
4162 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c4093 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_HDMI_init()
4162 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c4102 MDrv_WriteByteMask(REG_COMBO_GP_TOP_07_L, 0x00, 0xFF); // misc clock enable in Hal_HDMI_init()

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