Home
last modified time | relevance | path

Searched refs:REG_CKG_PDW0 (Results 1 – 25 of 27) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_dip.c1187 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_INVERT); // Not Invert in HAL_XC_DIP_Init()
1188 …MDrv_DIP_WriteRegBit(REG_CKG_PDW0, CKG_PDW0_GATED, CKG_PDW0_GATED); // Disable … in HAL_XC_DIP_Init()
1292 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_EnableCaptureStream()
1457 …MDrv_DIP_WriteRegBit(REG_CKG_PDW0, CKG_PDW0_GATED, CKG_PDW0_GATED); // Disable … in HAL_XC_DIP_ClearIntr()
1562 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_CpatureOneFrame2()
1929 MDrv_DIP_WriteByteMask(REG_CKG_PDW0, u8Clk_Mux, CKG_PDW0_MASK); in HAL_XC_DIP_SetMux()
3307 …MDrv_DIP_WriteRegBit(REG_CKG_PDW0, CKG_PDW0_GATED, CKG_PDW0_GATED); // Disable … in HAL_XC_DIP_InterruptDetach()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_dip.c1188 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_INVERT); // Not Invert in HAL_XC_DIP_Init()
1189 …MDrv_DIP_WriteRegBit(REG_CKG_PDW0, CKG_PDW0_GATED, CKG_PDW0_GATED); // Disable … in HAL_XC_DIP_Init()
1293 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_EnableCaptureStream()
1458 …MDrv_DIP_WriteRegBit(REG_CKG_PDW0, CKG_PDW0_GATED, CKG_PDW0_GATED); // Disable … in HAL_XC_DIP_ClearIntr()
1563 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_CpatureOneFrame2()
1930 MDrv_DIP_WriteByteMask(REG_CKG_PDW0, u8Clk_Mux, CKG_PDW0_MASK); in HAL_XC_DIP_SetMux()
3309 …MDrv_DIP_WriteRegBit(REG_CKG_PDW0, CKG_PDW0_GATED, CKG_PDW0_GATED); // Disable … in HAL_XC_DIP_InterruptDetach()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_dip.c1470 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_INVERT); // Not Invert in HAL_XC_DIP_Init()
1471 …MDrv_DIP_WriteRegBit(REG_CKG_PDW0, CKG_PDW0_GATED, CKG_PDW0_GATED); // Disab… in HAL_XC_DIP_Init()
1559 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_EnableCaptureStream()
1754 …MDrv_WriteRegBit(REG_CKG_PDW0, CKG_PDW0_GATED, CKG_PDW0_GATED); // Disable clock in HAL_XC_DIP_ClearIntr()
1846 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_CpatureOneFrame2()
2167 MDrv_DIP_WriteByteMask(REG_CKG_PDW0, u8Clk_Mux, CKG_PDW0_MASK); in HAL_XC_DIP_SetMux()
4258 …MDrv_WriteRegBit(REG_CKG_PDW0, CKG_PDW0_GATED, CKG_PDW0_GATED); // Disable clock in HAL_XC_DIP_InterruptDetach()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_dip.c483 MDrv_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_INVERT); // Not Invert in HAL_XC_DIP_Init()
484 MDrv_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_Init()
1008 W2BYTEMSK(REG_CKG_PDW0, u16Clk_Mux , CKG_PDW0_MASK); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_dip.c502 MDrv_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_INVERT); // Not Invert in HAL_XC_DIP_Init()
503 MDrv_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_Init()
1027 W2BYTEMSK(REG_CKG_PDW0, u16Clk_Mux , CKG_PDW0_MASK); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_dip.c656 MDrv_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_INVERT); // Not Invert in HAL_XC_DIP_Init()
657 MDrv_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_Init()
1280 MDrv_WriteByteMask(REG_CKG_PDW0, u8Clk_Mux, CKG_PDW0_MASK); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_dip.c808 MDrv_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_INVERT); // Not Invert in HAL_XC_DIP_Init()
809 MDrv_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_Init()
1426 MDrv_WriteByteMask(REG_CKG_PDW0, u8Clk_Mux, CKG_PDW0_MASK); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_dip.c766 MDrv_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_INVERT); // Not Invert in HAL_XC_DIP_Init()
767 MDrv_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_Init()
1402 MDrv_WriteByteMask(REG_CKG_PDW0, u8Clk_Mux, CKG_PDW0_MASK); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_dip.c768 MDrv_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_INVERT); // Not Invert in HAL_XC_DIP_Init()
769 MDrv_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_Init()
1404 MDrv_WriteByteMask(REG_CKG_PDW0, u8Clk_Mux, CKG_PDW0_MASK); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_dip.c689 MDrv_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_INVERT); // Not Invert in HAL_XC_DIP_Init()
690 MDrv_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_Init()
1315 MDrv_WriteByteMask(REG_CKG_PDW0, u8Clk_Mux, CKG_PDW0_MASK); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dmhal_xc_chip_config.h604 #define REG_CKG_PDW0 (REG_CLKGEN0_BASE + (0x5F<<1) ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dmhal_xc_chip_config.h604 #define REG_CKG_PDW0 (REG_CLKGEN0_BASE + (0x5F<<1) ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_dip.c1188 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_INVERT); // Not Invert in HAL_XC_DIP_Init()
1189 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_Init()
1895 MDrv_DIP_WriteByteMask(REG_CKG_PDW0, u8Clk_Mux, CKG_PDW0_MASK); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_dip.c1188 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_INVERT); // Not Invert in HAL_XC_DIP_Init()
1189 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_Init()
1895 MDrv_DIP_WriteByteMask(REG_CKG_PDW0, u8Clk_Mux, CKG_PDW0_MASK); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_dip.c1417 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_INVERT); // Not Invert in HAL_XC_DIP_Init()
1418 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_Init()
2048 MDrv_DIP_WriteByteMask(REG_CKG_PDW0, u8Clk_Mux, CKG_PDW0_MASK); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dmhal_xc_chip_config.h891 #define REG_CKG_PDW0 (REG_CHIPTOP_BASE + (0x5B<<1) ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dmhal_xc_chip_config.h897 #define REG_CKG_PDW0 (REG_CHIPTOP_BASE + (0x5B<<1) ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dmhal_xc_chip_config.h890 #define REG_CKG_PDW0 (REG_CHIPTOP_BASE + (0x5B<<1) ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dmhal_xc_chip_config.h884 #define REG_CKG_PDW0 (REG_CHIPTOP_BASE + (0x5B<<1) ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_xc_chip_config.h758 #define REG_CKG_PDW0 (REG_CLKGEN0_BASE + 0xBE ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_xc_chip_config.h865 #define REG_CKG_PDW0 (REG_CLKGEN0_BASE + 0xBE ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_xc_chip_config.h826 #define REG_CKG_PDW0 (REG_CLKGEN0_BASE + 0xBE ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_xc_chip_config.h877 #define REG_CKG_PDW0 (REG_CLKGEN0_BASE + 0xBE ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_xc_chip_config.h812 #define REG_CKG_PDW0 (REG_CLKGEN0_BASE + 0xBE ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_xc_chip_config.h882 #define REG_CKG_PDW0 (REG_CLKGEN0_BASE + 0xBE ) macro

12