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Searched refs:REG_CKG_FCLK (Results 1 – 25 of 64) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_sc.c4936 MS_U8 u8FClkReg = MDrv_ReadByte(REG_CKG_FCLK) & CKG_FCLK_MASK; in _Hal_SC_get_Fclk()
4987 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4995 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_320MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5000 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5026 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5033 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5045 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5053 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5060 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_320MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5077 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
[all …]
H A Dmhal_dip.c881 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_320MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
943 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_216MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
2873 u16tmp = MDrv_ReadByte(REG_CKG_FCLK)&CKG_FCLK_MASK; in HAL_XC_DIP_Check_Clock()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_sc.c4775 MS_U8 u8FClkReg = MDrv_ReadByte(REG_CKG_FCLK) & CKG_FCLK_MASK; in _Hal_SC_get_Fclk()
4826 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4834 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_320MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4839 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4865 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4872 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4884 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4892 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4899 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_320MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4916 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
[all …]
H A Dmhal_dip.c879 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_320MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
941 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_216MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
2891 u16tmp = MDrv_ReadByte(REG_CKG_FCLK)&CKG_FCLK_MASK; in HAL_XC_DIP_Check_Clock()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_sc.c5086 u8FClkReg = MDrv_ReadByte(REG_CKG_FCLK) & CKG_FCLK_MASK; in _Hal_SC_get_Fclk()
5166 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5174 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_320MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5179 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5215 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5222 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5234 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5242 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5249 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_320MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5266 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
[all …]
/utopia/UTPA2-700.0.x/modules/pws/hal/maldives/pws/
H A DregCLKGEN.h333 #define REG_CKG_FCLK 0x1E35 macro
/utopia/UTPA2-700.0.x/modules/pws/hal/k6/pws/
H A DregCLKGEN.h333 #define REG_CKG_FCLK 0x1E35 macro
/utopia/UTPA2-700.0.x/modules/pws/hal/macan/pws/
H A DregCLKGEN.h333 #define REG_CKG_FCLK 0x1E35UL macro
/utopia/UTPA2-700.0.x/modules/pws/hal/mooney/pws/
H A DregCLKGEN.h333 #define REG_CKG_FCLK 0x1E35UL macro
/utopia/UTPA2-700.0.x/modules/pws/hal/messi/pws/
H A DregCLKGEN.h333 #define REG_CKG_FCLK 0x1E35UL macro
/utopia/UTPA2-700.0.x/modules/pws/hal/manhattan/pws/
H A DregCLKGEN.h333 #define REG_CKG_FCLK 0x1E35UL macro
/utopia/UTPA2-700.0.x/modules/pws/hal/k6lite/pws/
H A DregCLKGEN.h333 #define REG_CKG_FCLK 0x1E35 macro
/utopia/UTPA2-700.0.x/modules/pws/hal/M7821/pws/
H A DregCLKGEN.h333 #define REG_CKG_FCLK 0x1E35UL macro
/utopia/UTPA2-700.0.x/modules/pws/hal/mainz/pws/
H A DregCLKGEN.h333 #define REG_CKG_FCLK 0x1E35UL macro
/utopia/UTPA2-700.0.x/modules/pws/hal/mustang/pws/
H A DregCLKGEN.h333 #define REG_CKG_FCLK 0x1E35 macro
/utopia/UTPA2-700.0.x/modules/pws/hal/maxim/pws/
H A DregCLKGEN.h333 #define REG_CKG_FCLK 0x1E35UL macro
/utopia/UTPA2-700.0.x/modules/pws/hal/M7621/pws/
H A DregCLKGEN.h333 #define REG_CKG_FCLK 0x1E35UL macro
/utopia/UTPA2-700.0.x/modules/pws/hal/curry/pws/
H A DregCLKGEN.h333 #define REG_CKG_FCLK 0x1E35 macro
/utopia/UTPA2-700.0.x/modules/pws/hal/kano/pws/
H A DregCLKGEN.h333 #define REG_CKG_FCLK 0x1E35 macro
/utopia/UTPA2-700.0.x/modules/pws/hal/maserati/pws/
H A DregCLKGEN.h333 #define REG_CKG_FCLK 0x1E35UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dmhal_xc_chip_config.h509 #define REG_CKG_FCLK (REG_CLKGEN0_BASE + 0xA5 ) // after memory, before fodclk macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dmhal_xc_chip_config.h509 #define REG_CKG_FCLK (REG_CLKGEN0_BASE + 0xA5 ) // after memory, before fodclk macro
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/
H A Dmvideo.c497 … MDrv_WriteRegBit(REG_CKG_FCLK, ENABLE, CKG_FCLK_GATED); // Enable clock in MApi_XC_Exit_U2()
545 … MDrv_WriteRegBit(REG_CKG_FCLK, ENABLE, CKG_FCLK_GATED); // Enable clock in MApi_XC_Exit_U2()
585 … MDrv_WriteRegBit(REG_CKG_FCLK, ENABLE, CKG_FCLK_GATED); // Enable clock in MApi_XC_Exit_U2()
1137 …MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_170MHZ, CKG_FCLK_MASK); // select 170M… in _MApi_XC_Init_WithoutCreateMutex()
1138 … MDrv_WriteRegBit(REG_CKG_FCLK, DISABLE, CKG_FCLK_INVERT); // Not Invert in _MApi_XC_Init_WithoutCreateMutex()
1139 …MDrv_WriteRegBit(REG_CKG_FCLK, DISABLE, CKG_FCLK_GATED); // Enable clock in _MApi_XC_Init_WithoutCreateMutex()
1181 …MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_DEFAULT, CKG_FCLK_MASK); // select 170… in _MApi_XC_Init_WithoutCreateMutex()
1182 … MDrv_WriteRegBit(REG_CKG_FCLK, DISABLE, CKG_FCLK_INVERT); // Not Invert in _MApi_XC_Init_WithoutCreateMutex()
1183 …MDrv_WriteRegBit(REG_CKG_FCLK, DISABLE, CKG_FCLK_GATED); // Enable clock in _MApi_XC_Init_WithoutCreateMutex()
1215 …MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_DEFAULT, CKG_FCLK_MASK); // select 170… in _MApi_XC_Init_WithoutCreateMutex()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dmhal_xc_chip_config.h664 #define REG_CKG_FCLK (REG_CLKGEN0_BASE + 0xA5 ) // after memory, before fodclk macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dmhal_xc_chip_config.h662 #define REG_CKG_FCLK (REG_CLKGEN0_BASE + 0xA5 ) // after memory, before fodclk macro

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