| /utopia/UTPA2-700.0.x/modules/mvop/hal/maldives/mvop/ |
| H A D | halMVOP.c | 556 HAL_WriteByteMask(REG_CKG_DC0, 0, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
560 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_SYNCHRONOUS, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
563 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_FREERUN, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
566 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_160MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
569 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_144MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
572 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_SYNCHRONOUS, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
1172 HAL_WriteRegBit(REG_CKG_DC0, !bEnable, CKG_DC0_GATED); in HAL_MVOP_SetDCClk()
|
| /utopia/UTPA2-700.0.x/modules/mvop/hal/curry/mvop/ |
| H A D | halMVOP.c | 719 HAL_WriteByteMask(REG_CKG_DC0, 0, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
723 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_SYNCHRONOUS, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
726 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_FREERUN, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
729 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_320MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
732 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_108MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
735 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_123MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
738 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_144MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
741 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_160MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
744 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_192MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
747 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_160MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/mvop/hal/k7u/mvop/ |
| H A D | halMVOP.c | 709 HAL_WriteByteMask(REG_CKG_DC0, 0, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
713 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_SYNCHRONOUS, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
716 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_FREERUN, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
719 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_320MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
722 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_345MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
725 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_123MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
728 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_144MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
731 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_160MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
734 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_192MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
737 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_160MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/mvop/hal/k6/mvop/ |
| H A D | halMVOP.c | 701 HAL_WriteByteMask(REG_CKG_DC0, 0, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
705 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_SYNCHRONOUS, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
708 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_FREERUN, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
711 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_320MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
714 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_108MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
717 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_123MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
720 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_144MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
723 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_160MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
726 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_192MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
729 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_160MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/mvop/hal/kastor/mvop/ |
| H A D | halMVOP.c | 718 HAL_WriteByteMask(REG_CKG_DC0, 0, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
722 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_SYNCHRONOUS, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
725 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_FREERUN, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
728 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_320MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
731 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_108MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
734 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_123MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
737 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_144MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
740 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_160MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
743 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_192MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
746 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_160MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/mvop/hal/kano/mvop/ |
| H A D | halMVOP.c | 721 HAL_WriteByteMask(REG_CKG_DC0, 0, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
725 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_SYNCHRONOUS, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
728 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_FREERUN, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
731 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_320MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
734 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_108MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
737 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_123MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
740 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_144MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
743 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_160MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
746 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_192MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
749 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_160MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/mvop/hal/k6lite/mvop/ |
| H A D | halMVOP.c | 694 HAL_WriteByteMask(REG_CKG_DC0, 0, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
698 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_SYNCHRONOUS, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
701 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_FREERUN, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
709 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_108MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
712 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_123MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
715 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_144MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
718 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_160MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
721 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_192MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
724 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_160MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
740 u8DC0Clk = HAL_ReadByte(REG_CKG_DC0)&CKG_DC0_MASK; in HAL_MVOP_GetCurrentClk()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/mvop/hal/manhattan/mvop/ |
| H A D | halMVOP.c | 710 HAL_WriteByteMask(REG_CKG_DC0, 0, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
714 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_SYNCHRONOUS, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
717 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_FREERUN, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
720 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_160MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
723 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_144MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
726 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_320MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
729 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_SYNCHRONOUS, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
1398 HAL_WriteRegBit(REG_CKG_DC0, !bEnable, CKG_DC0_GATED); in HAL_MVOP_SetDCClk()
3451 u16Reg = HAL_Read2Byte(CHIP_REG_BASE + REG_CKG_DC0 + u16Length); in HAL_MVOP_ReadClkBank()
3477 HAL_Write2Byte((CHIP_REG_BASE + REG_CKG_DC0 + u16Length), u16Data); in HAL_MVOP_WriteClkBank()
|
| /utopia/UTPA2-700.0.x/modules/mvop/hal/maserati/mvop/ |
| H A D | halMVOP.c | 744 HAL_WriteByteMask(REG_CKG_DC0, 0, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
748 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_SYNCHRONOUS, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
751 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_FREERUN, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
754 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_160MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
757 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_144MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
760 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_320MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
763 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_SYNCHRONOUS, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
1490 HAL_WriteRegBit(REG_CKG_DC0, !bEnable, CKG_DC0_GATED); in HAL_MVOP_SetDCClk()
3615 u16Reg = HAL_Read2Byte(REG_CKG_DC0 + (u16Length << 1)); // main/sub sram in HAL_MVOP_ReadClkBank()
3639 HAL_Write2Byte(REG_CKG_DC0 + (u16Length << 1), u16Data); in HAL_MVOP_WriteClkBank()
|
| /utopia/UTPA2-700.0.x/modules/mvop/hal/M7621/mvop/ |
| H A D | halMVOP.c | 746 HAL_WriteByteMask(REG_CKG_DC0, 0, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
750 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_SYNCHRONOUS, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
753 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_FREERUN, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
756 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_160MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
759 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_144MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
762 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_320MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
765 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_SYNCHRONOUS, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
1491 HAL_WriteRegBit(REG_CKG_DC0, !bEnable, CKG_DC0_GATED); in HAL_MVOP_SetDCClk()
3596 u16Reg = HAL_Read2Byte(REG_CKG_DC0 + (u16Length << 1)); // main/sub sram in HAL_MVOP_ReadClkBank()
3620 HAL_Write2Byte(REG_CKG_DC0 + (u16Length << 1), u16Data); in HAL_MVOP_WriteClkBank()
|
| /utopia/UTPA2-700.0.x/modules/mvop/hal/M7821/mvop/ |
| H A D | halMVOP.c | 742 HAL_WriteByteMask(REG_CKG_DC0, 0, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
746 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_SYNCHRONOUS, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
749 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_FREERUN, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
752 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_160MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
755 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_144MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
758 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_320MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
761 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_SYNCHRONOUS, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
1482 HAL_WriteRegBit(REG_CKG_DC0, !bEnable, CKG_DC0_GATED); in HAL_MVOP_SetDCClk()
3585 u16Reg = HAL_Read2Byte(REG_CKG_DC0 + (u16Length << 1)); // main/sub sram in HAL_MVOP_ReadClkBank()
3609 HAL_Write2Byte(REG_CKG_DC0 + (u16Length << 1), u16Data); in HAL_MVOP_WriteClkBank()
|
| /utopia/UTPA2-700.0.x/modules/mvop/hal/M5621/mvop/ |
| H A D | halMVOP.c | 668 HAL_WriteByteMask(REG_CKG_DC0, 0, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
672 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_SYNCHRONOUS, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
675 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_FREERUN, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
678 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_160MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
681 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_144MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
684 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_SYNCHRONOUS, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
1371 HAL_WriteRegBit(REG_CKG_DC0, !bEnable, CKG_DC0_GATED); in HAL_MVOP_SetDCClk()
3155 u16Reg = HAL_Read2Byte(REG_CKG_DC0 + (u16Length << 1)); // main/sub sram in HAL_MVOP_ReadClkBank()
3177 HAL_Write2Byte(REG_CKG_DC0 + (u16Length << 1), u16Data); in HAL_MVOP_WriteClkBank()
|
| /utopia/UTPA2-700.0.x/modules/mvop/hal/maxim/mvop/ |
| H A D | halMVOP.c | 759 HAL_WriteByteMask(REG_CKG_DC0, 0, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
763 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_SYNCHRONOUS, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
766 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_FREERUN, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
769 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_160MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
772 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_144MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
775 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_320MHZ, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
778 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_SYNCHRONOUS, CKG_DC0_MASK); in HAL_MVOP_SetFrequency()
1512 HAL_WriteRegBit(REG_CKG_DC0, !bEnable, CKG_DC0_GATED); in HAL_MVOP_SetDCClk()
3657 u16Reg = HAL_Read2Byte(REG_CKG_DC0 + (u16Length << 1)); // main/sub sram in HAL_MVOP_ReadClkBank()
3681 HAL_Write2Byte(REG_CKG_DC0 + (u16Length << 1), u16Data); in HAL_MVOP_WriteClkBank()
|
| /utopia/UTPA2-700.0.x/modules/pws/hal/maldives/pws/ |
| H A D | regCLKGEN.h | 193 #define REG_CKG_DC0 0x1E2A macro
514 #define REG_CKG_AEON1DC0 REG_CKG_DC0
|
| /utopia/UTPA2-700.0.x/modules/pws/hal/k6/pws/ |
| H A D | regCLKGEN.h | 193 #define REG_CKG_DC0 0x1E2A macro
514 #define REG_CKG_AEON1DC0 REG_CKG_DC0
|
| /utopia/UTPA2-700.0.x/modules/pws/hal/macan/pws/ |
| H A D | regCLKGEN.h | 193 #define REG_CKG_DC0 0x1E2AUL macro
514 #define REG_CKG_AEON1DC0 REG_CKG_DC0
|
| /utopia/UTPA2-700.0.x/modules/pws/hal/mooney/pws/ |
| H A D | regCLKGEN.h | 193 #define REG_CKG_DC0 0x1E2AUL macro
514 #define REG_CKG_AEON1DC0 REG_CKG_DC0
|
| /utopia/UTPA2-700.0.x/modules/pws/hal/messi/pws/ |
| H A D | regCLKGEN.h | 193 #define REG_CKG_DC0 0x1E2AUL macro
514 #define REG_CKG_AEON1DC0 REG_CKG_DC0
|
| /utopia/UTPA2-700.0.x/modules/pws/hal/manhattan/pws/ |
| H A D | regCLKGEN.h | 193 #define REG_CKG_DC0 0x1E2AUL macro
514 #define REG_CKG_AEON1DC0 REG_CKG_DC0
|
| /utopia/UTPA2-700.0.x/modules/pws/hal/k6lite/pws/ |
| H A D | regCLKGEN.h | 193 #define REG_CKG_DC0 0x1E2A macro
514 #define REG_CKG_AEON1DC0 REG_CKG_DC0
|
| /utopia/UTPA2-700.0.x/modules/pws/hal/M7821/pws/ |
| H A D | regCLKGEN.h | 193 #define REG_CKG_DC0 0x1E2AUL macro
514 #define REG_CKG_AEON1DC0 REG_CKG_DC0
|
| /utopia/UTPA2-700.0.x/modules/pws/hal/mainz/pws/ |
| H A D | regCLKGEN.h | 193 #define REG_CKG_DC0 0x1E2AUL macro
514 #define REG_CKG_AEON1DC0 REG_CKG_DC0
|
| /utopia/UTPA2-700.0.x/modules/pws/hal/mustang/pws/ |
| H A D | regCLKGEN.h | 193 #define REG_CKG_DC0 0x1E2A macro
514 #define REG_CKG_AEON1DC0 REG_CKG_DC0
|
| /utopia/UTPA2-700.0.x/modules/pws/hal/maxim/pws/ |
| H A D | regCLKGEN.h | 193 #define REG_CKG_DC0 0x1E2AUL macro
514 #define REG_CKG_AEON1DC0 REG_CKG_DC0
|
| /utopia/UTPA2-700.0.x/modules/pws/hal/M7621/pws/ |
| H A D | regCLKGEN.h | 193 #define REG_CKG_DC0 0x1E2AUL macro
514 #define REG_CKG_AEON1DC0 REG_CKG_DC0
|