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Searched refs:REG_CHIPTOP_BASE (Results 1 – 25 of 107) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dmhal_xc_chip_config.h507 #define REG_CHIPTOP_BASE 0x100B00 // 0x1E00 - 0x1EFF macro
627 #define REG_CKG_DACA2 (REG_CHIPTOP_BASE + 0x4C ) //DAC out
636 #define REG_CKG_DACB2 (REG_CHIPTOP_BASE + 0x4D ) //DAC out
645 #define REG_CKG_FMCLK (REG_CHIPTOP_BASE + 0xBB )
653 #define REG_CKG_SC_ROT (REG_CHIPTOP_BASE + 0xFF )
660 #define REG_CKG_FICLK_F1 (REG_CHIPTOP_BASE + 0xA2 ) // scaling line buffer, set to fclk if p…
667 #define REG_CKG_FICLK_F2 (REG_CHIPTOP_BASE + 0xA3 ) // scaling line buffer, set to fclk if p…
674 #define REG_CKG_FICLK2_F2 (REG_CHIPTOP_BASE + 0xA3 ) // scaling line buffer, set to fclk if p…
681 #define REG_CKG_FCLK (REG_CHIPTOP_BASE + 0xA5 ) // after memory, before fodclk
694 #define REG_CKG_EDCLK (REG_CHIPTOP_BASE + 0xB7 ) // after memory, before fodclk
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dmhal_xc_chip_config.h509 #define REG_CHIPTOP_BASE 0x100B00 // 0x1E00 - 0x1EFF macro
629 #define REG_CKG_DACA2 (REG_CHIPTOP_BASE + 0x4C ) //DAC out
638 #define REG_CKG_DACB2 (REG_CHIPTOP_BASE + 0x4D ) //DAC out
647 #define REG_CKG_FMCLK (REG_CHIPTOP_BASE + 0xBB )
655 #define REG_CKG_SC_ROT (REG_CHIPTOP_BASE + 0xFF )
662 #define REG_CKG_FICLK_F1 (REG_CHIPTOP_BASE + 0xA2 ) // scaling line buffer, set to fclk if p…
669 #define REG_CKG_FICLK_F2 (REG_CHIPTOP_BASE + 0xA3 ) // scaling line buffer, set to fclk if p…
676 #define REG_CKG_FICLK2_F2 (REG_CHIPTOP_BASE + 0xA3 ) // scaling line buffer, set to fclk if p…
683 #define REG_CKG_FCLK (REG_CHIPTOP_BASE + 0xA5 ) // after memory, before fodclk
693 #define REG_CKG_EDCLK (REG_CHIPTOP_BASE + 0xB7 ) // after memory, before fodclk
[all …]
H A Dmhal_xc_chip_config.h.0508 #define REG_CHIPTOP_BASE 0x100B00 // 0x1E00 - 0x1EFF
628 #define REG_CKG_DACA2 (REG_CHIPTOP_BASE + 0x4C ) //DAC out
637 #define REG_CKG_DACB2 (REG_CHIPTOP_BASE + 0x4D ) //DAC out
646 #define REG_CKG_FMCLK (REG_CHIPTOP_BASE + 0xBB )
654 #define REG_CKG_SC_ROT (REG_CHIPTOP_BASE + 0xFF )
661 #define REG_CKG_FICLK_F1 (REG_CHIPTOP_BASE + 0xA2 ) // scaling line buffer, set to fclk if p…
668 #define REG_CKG_FICLK_F2 (REG_CHIPTOP_BASE + 0xA3 ) // scaling line buffer, set to fclk if p…
675 #define REG_CKG_FICLK2_F2 (REG_CHIPTOP_BASE + 0xA3 ) // scaling line buffer, set to fclk if p…
682 #define REG_CKG_FCLK (REG_CHIPTOP_BASE + 0xA5 ) // after memory, before fodclk
692 #define REG_CKG_EDCLK (REG_CHIPTOP_BASE + 0xB7 ) // after memory, before fodclk
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dmhal_xc_chip_config.h501 #define REG_CHIPTOP_BASE 0x100B00 // 0x1E00 - 0x1EFF macro
621 #define REG_CKG_DACA2 (REG_CHIPTOP_BASE + 0x4C ) //DAC out
630 #define REG_CKG_DACB2 (REG_CHIPTOP_BASE + 0x4D ) //DAC out
639 #define REG_CKG_FMCLK (REG_CHIPTOP_BASE + 0xBB )
647 #define REG_CKG_SC_ROT (REG_CHIPTOP_BASE + 0xFF )
654 #define REG_CKG_FICLK_F1 (REG_CHIPTOP_BASE + 0xA2 ) // scaling line buffer, set to fclk if p…
661 #define REG_CKG_FICLK_F2 (REG_CHIPTOP_BASE + 0xA3 ) // scaling line buffer, set to fclk if p…
668 #define REG_CKG_FICLK2_F2 (REG_CHIPTOP_BASE + 0xA3 ) // scaling line buffer, set to fclk if p…
675 #define REG_CKG_FCLK (REG_CHIPTOP_BASE + 0xA5 ) // after memory, before fodclk
688 #define REG_CKG_EDCLK (REG_CHIPTOP_BASE + 0xB7 ) // after memory, before fodclk
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dmhal_xc_chip_config.h507 #define REG_CHIPTOP_BASE 0x100B00 // 0x1E00 - 0x1EFF macro
627 #define REG_CKG_DACA2 (REG_CHIPTOP_BASE + 0x4C ) //DAC out
636 #define REG_CKG_DACB2 (REG_CHIPTOP_BASE + 0x4D ) //DAC out
645 #define REG_CKG_FMCLK (REG_CHIPTOP_BASE + 0xBB )
653 #define REG_CKG_SC_ROT (REG_CHIPTOP_BASE + 0xFF )
660 #define REG_CKG_FICLK_F1 (REG_CHIPTOP_BASE + 0xA2 ) // scaling line buffer, set to fclk if p…
667 #define REG_CKG_FICLK_F2 (REG_CHIPTOP_BASE + 0xA3 ) // scaling line buffer, set to fclk if p…
674 #define REG_CKG_FICLK2_F2 (REG_CHIPTOP_BASE + 0xA3 ) // scaling line buffer, set to fclk if p…
681 #define REG_CKG_FCLK (REG_CHIPTOP_BASE + 0xA5 ) // after memory, before fodclk
694 #define REG_CKG_EDCLK (REG_CHIPTOP_BASE + 0xB7 ) // after memory, before fodclk
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/macan/mvd_ex/
H A DregMVD_EX.h203 #define REG_CHIPTOP_BASE 0x0b00UL macro
205 #define REG_CKG_MVD_SYNC (REG_CHIPTOP_BASE + 0x38*2 +1)
208 #define REG_CKG_MVD (REG_CHIPTOP_BASE + 0x39*2)
221 #define REG_CKG_MVD2 (REG_CHIPTOP_BASE + 0x39*2 +1)
234 #define REG_CKG_MVD_CHROMA_A (REG_CHIPTOP_BASE + 0x3d*2)
238 #define REG_CKG_MVD_CHROMA_B (REG_CHIPTOP_BASE + 0x3d*2)
242 #define REG_CKG_MVD_CHROMA_C (REG_CHIPTOP_BASE + 0x3d*2 + 1)
246 #define REG_CKG_MVD_LUMA_A (REG_CHIPTOP_BASE + 0x3a*2 + 1)
250 #define REG_CKG_MVD_LUMA_B (REG_CHIPTOP_BASE + 0x3b*2)
254 #define REG_CKG_MVD_LUMA_C (REG_CHIPTOP_BASE + 0x3b*2 + 1)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maxim/mvd/
H A DregMVD.h214 #define REG_CHIPTOP_BASE 0x0b00 macro
216 #define REG_CKG_MVD_SYNC (REG_CHIPTOP_BASE + 0x38*2 +1)
219 #define REG_CKG_MVD (REG_CHIPTOP_BASE + 0x39*2)
232 #define REG_CKG_MVD2 (REG_CHIPTOP_BASE + 0x39*2 +1)
245 #define REG_CKG_MVD_CHROMA_A (REG_CHIPTOP_BASE + 0x3d*2)
249 #define REG_CKG_MVD_CHROMA_B (REG_CHIPTOP_BASE + 0x3d*2)
253 #define REG_CKG_MVD_CHROMA_C (REG_CHIPTOP_BASE + 0x3d*2 + 1)
257 #define REG_CKG_MVD_LUMA_A (REG_CHIPTOP_BASE + 0x3a*2 + 1)
261 #define REG_CKG_MVD_LUMA_B (REG_CHIPTOP_BASE + 0x3b*2)
265 #define REG_CKG_MVD_LUMA_C (REG_CHIPTOP_BASE + 0x3b*2 + 1)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mustang/mvd_ex/
H A DregMVD_EX.h203 #define REG_CHIPTOP_BASE 0x0b00 macro
205 #define REG_CKG_MVD_SYNC (REG_CHIPTOP_BASE + 0x38*2 +1)
208 #define REG_CKG_MVD (REG_CHIPTOP_BASE + 0x39*2)
219 #define REG_CKG_MVD2 (REG_CHIPTOP_BASE + 0x39*2 +1)
229 #define REG_CKG_MVD_CHROMA_A (REG_CHIPTOP_BASE + 0x3d*2)
233 #define REG_CKG_MVD_CHROMA_B (REG_CHIPTOP_BASE + 0x3d*2)
237 #define REG_CKG_MVD_CHROMA_C (REG_CHIPTOP_BASE + 0x3d*2 + 1)
241 #define REG_CKG_MVD_LUMA_A (REG_CHIPTOP_BASE + 0x3a*2 + 1)
245 #define REG_CKG_MVD_LUMA_B (REG_CHIPTOP_BASE + 0x3b*2)
249 #define REG_CKG_MVD_LUMA_C (REG_CHIPTOP_BASE + 0x3b*2 + 1)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/mainz/mvd/
H A DregMVD.h214 #define REG_CHIPTOP_BASE 0x0b00 macro
216 #define REG_CKG_MVD_SYNC (REG_CHIPTOP_BASE + 0x38*2 +1)
219 #define REG_CKG_MVD (REG_CHIPTOP_BASE + 0x39*2)
232 #define REG_CKG_MVD2 (REG_CHIPTOP_BASE + 0x39*2 +1)
245 #define REG_CKG_MVD_CHROMA_A (REG_CHIPTOP_BASE + 0x3d*2)
249 #define REG_CKG_MVD_CHROMA_B (REG_CHIPTOP_BASE + 0x3d*2)
253 #define REG_CKG_MVD_CHROMA_C (REG_CHIPTOP_BASE + 0x3d*2 + 1)
257 #define REG_CKG_MVD_LUMA_A (REG_CHIPTOP_BASE + 0x3a*2 + 1)
261 #define REG_CKG_MVD_LUMA_B (REG_CHIPTOP_BASE + 0x3b*2)
265 #define REG_CKG_MVD_LUMA_C (REG_CHIPTOP_BASE + 0x3b*2 + 1)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maserati/mvd/
H A DregMVD.h214 #define REG_CHIPTOP_BASE 0x0b00 macro
216 #define REG_CKG_MVD_SYNC (REG_CHIPTOP_BASE + 0x38*2 +1)
219 #define REG_CKG_MVD (REG_CHIPTOP_BASE + 0x39*2)
232 #define REG_CKG_MVD2 (REG_CHIPTOP_BASE + 0x39*2 +1)
245 #define REG_CKG_MVD_CHROMA_A (REG_CHIPTOP_BASE + 0x3d*2)
249 #define REG_CKG_MVD_CHROMA_B (REG_CHIPTOP_BASE + 0x3d*2)
253 #define REG_CKG_MVD_CHROMA_C (REG_CHIPTOP_BASE + 0x3d*2 + 1)
257 #define REG_CKG_MVD_LUMA_A (REG_CHIPTOP_BASE + 0x3a*2 + 1)
261 #define REG_CKG_MVD_LUMA_B (REG_CHIPTOP_BASE + 0x3b*2)
265 #define REG_CKG_MVD_LUMA_C (REG_CHIPTOP_BASE + 0x3b*2 + 1)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/mvd_v3/
H A DregMVD_EX.h203 #define REG_CHIPTOP_BASE 0x0b00UL macro
205 #define REG_CKG_MVD_SYNC (REG_CHIPTOP_BASE + 0x38*2 +1)
208 #define REG_CKG_MVD (REG_CHIPTOP_BASE + 0x39*2)
221 #define REG_CKG_MVD2 (REG_CHIPTOP_BASE + 0x39*2 +1)
234 #define REG_CKG_MVD_CHROMA_A (REG_CHIPTOP_BASE + 0x3d*2)
238 #define REG_CKG_MVD_CHROMA_B (REG_CHIPTOP_BASE + 0x3d*2)
242 #define REG_CKG_MVD_CHROMA_C (REG_CHIPTOP_BASE + 0x3d*2 + 1)
246 #define REG_CKG_MVD_LUMA_A (REG_CHIPTOP_BASE + 0x3a*2 + 1)
250 #define REG_CKG_MVD_LUMA_B (REG_CHIPTOP_BASE + 0x3b*2)
254 #define REG_CKG_MVD_LUMA_C (REG_CHIPTOP_BASE + 0x3b*2 + 1)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7621/mvd_ex/
H A DregMVD_EX.h203 #define REG_CHIPTOP_BASE 0x0b00UL macro
205 #define REG_CKG_MVD_SYNC (REG_CHIPTOP_BASE + 0x38*2 +1)
208 #define REG_CKG_MVD (REG_CHIPTOP_BASE + 0x39*2)
221 #define REG_CKG_MVD2 (REG_CHIPTOP_BASE + 0x39*2 +1)
234 #define REG_CKG_MVD_CHROMA_A (REG_CHIPTOP_BASE + 0x3d*2)
238 #define REG_CKG_MVD_CHROMA_B (REG_CHIPTOP_BASE + 0x3d*2)
242 #define REG_CKG_MVD_CHROMA_C (REG_CHIPTOP_BASE + 0x3d*2 + 1)
246 #define REG_CKG_MVD_LUMA_A (REG_CHIPTOP_BASE + 0x3a*2 + 1)
250 #define REG_CKG_MVD_LUMA_B (REG_CHIPTOP_BASE + 0x3b*2)
254 #define REG_CKG_MVD_LUMA_C (REG_CHIPTOP_BASE + 0x3b*2 + 1)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maserati/mvd_ex/
H A DregMVD_EX.h203 #define REG_CHIPTOP_BASE 0x0b00UL macro
205 #define REG_CKG_MVD_SYNC (REG_CHIPTOP_BASE + 0x38*2 +1)
208 #define REG_CKG_MVD (REG_CHIPTOP_BASE + 0x39*2)
221 #define REG_CKG_MVD2 (REG_CHIPTOP_BASE + 0x39*2 +1)
234 #define REG_CKG_MVD_CHROMA_A (REG_CHIPTOP_BASE + 0x3d*2)
238 #define REG_CKG_MVD_CHROMA_B (REG_CHIPTOP_BASE + 0x3d*2)
242 #define REG_CKG_MVD_CHROMA_C (REG_CHIPTOP_BASE + 0x3d*2 + 1)
246 #define REG_CKG_MVD_LUMA_A (REG_CHIPTOP_BASE + 0x3a*2 + 1)
250 #define REG_CKG_MVD_LUMA_B (REG_CHIPTOP_BASE + 0x3b*2)
254 #define REG_CKG_MVD_LUMA_C (REG_CHIPTOP_BASE + 0x3b*2 + 1)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/macan/mvd/
H A DregMVD.h214 #define REG_CHIPTOP_BASE 0x0b00 macro
216 #define REG_CKG_MVD_SYNC (REG_CHIPTOP_BASE + 0x38*2 +1)
219 #define REG_CKG_MVD (REG_CHIPTOP_BASE + 0x39*2)
232 #define REG_CKG_MVD2 (REG_CHIPTOP_BASE + 0x39*2 +1)
245 #define REG_CKG_MVD_CHROMA_A (REG_CHIPTOP_BASE + 0x3d*2)
249 #define REG_CKG_MVD_CHROMA_B (REG_CHIPTOP_BASE + 0x3d*2)
253 #define REG_CKG_MVD_CHROMA_C (REG_CHIPTOP_BASE + 0x3d*2 + 1)
257 #define REG_CKG_MVD_LUMA_A (REG_CHIPTOP_BASE + 0x3a*2 + 1)
261 #define REG_CKG_MVD_LUMA_B (REG_CHIPTOP_BASE + 0x3b*2)
265 #define REG_CKG_MVD_LUMA_C (REG_CHIPTOP_BASE + 0x3b*2 + 1)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maxim/mvd_ex/
H A DregMVD_EX.h203 #define REG_CHIPTOP_BASE 0x0b00UL macro
205 #define REG_CKG_MVD_SYNC (REG_CHIPTOP_BASE + 0x38*2 +1)
208 #define REG_CKG_MVD (REG_CHIPTOP_BASE + 0x39*2)
221 #define REG_CKG_MVD2 (REG_CHIPTOP_BASE + 0x39*2 +1)
234 #define REG_CKG_MVD_CHROMA_A (REG_CHIPTOP_BASE + 0x3d*2)
238 #define REG_CKG_MVD_CHROMA_B (REG_CHIPTOP_BASE + 0x3d*2)
242 #define REG_CKG_MVD_CHROMA_C (REG_CHIPTOP_BASE + 0x3d*2 + 1)
246 #define REG_CKG_MVD_LUMA_A (REG_CHIPTOP_BASE + 0x3a*2 + 1)
250 #define REG_CKG_MVD_LUMA_B (REG_CHIPTOP_BASE + 0x3b*2)
254 #define REG_CKG_MVD_LUMA_C (REG_CHIPTOP_BASE + 0x3b*2 + 1)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maldives/mvd_v3/
H A DregMVD_EX.h203 #define REG_CHIPTOP_BASE 0x0b00 macro
205 #define REG_CKG_MVD_SYNC (REG_CHIPTOP_BASE + 0x38*2 +1)
208 #define REG_CKG_MVD (REG_CHIPTOP_BASE + 0x39*2)
221 #define REG_CKG_MVD2 (REG_CHIPTOP_BASE + 0x39*2 +1)
234 #define REG_CKG_MVD_CHROMA_A (REG_CHIPTOP_BASE + 0x3d*2)
238 #define REG_CKG_MVD_CHROMA_B (REG_CHIPTOP_BASE + 0x3d*2)
242 #define REG_CKG_MVD_CHROMA_C (REG_CHIPTOP_BASE + 0x3d*2 + 1)
246 #define REG_CKG_MVD_LUMA_A (REG_CHIPTOP_BASE + 0x3a*2 + 1)
250 #define REG_CKG_MVD_LUMA_B (REG_CHIPTOP_BASE + 0x3b*2)
254 #define REG_CKG_MVD_LUMA_C (REG_CHIPTOP_BASE + 0x3b*2 + 1)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/messi/mvd/
H A DregMVD.h214 #define REG_CHIPTOP_BASE 0x0b00 macro
216 #define REG_CKG_MVD_SYNC (REG_CHIPTOP_BASE + 0x38*2 +1)
219 #define REG_CKG_MVD (REG_CHIPTOP_BASE + 0x39*2)
232 #define REG_CKG_MVD2 (REG_CHIPTOP_BASE + 0x39*2 +1)
245 #define REG_CKG_MVD_CHROMA_A (REG_CHIPTOP_BASE + 0x3d*2)
249 #define REG_CKG_MVD_CHROMA_B (REG_CHIPTOP_BASE + 0x3d*2)
253 #define REG_CKG_MVD_CHROMA_C (REG_CHIPTOP_BASE + 0x3d*2 + 1)
257 #define REG_CKG_MVD_LUMA_A (REG_CHIPTOP_BASE + 0x3a*2 + 1)
261 #define REG_CKG_MVD_LUMA_B (REG_CHIPTOP_BASE + 0x3b*2)
265 #define REG_CKG_MVD_LUMA_C (REG_CHIPTOP_BASE + 0x3b*2 + 1)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/manhattan/mvd/
H A DregMVD.h214 #define REG_CHIPTOP_BASE 0x0b00 macro
216 #define REG_CKG_MVD_SYNC (REG_CHIPTOP_BASE + 0x38*2 +1)
219 #define REG_CKG_MVD (REG_CHIPTOP_BASE + 0x39*2)
232 #define REG_CKG_MVD2 (REG_CHIPTOP_BASE + 0x39*2 +1)
245 #define REG_CKG_MVD_CHROMA_A (REG_CHIPTOP_BASE + 0x3d*2)
249 #define REG_CKG_MVD_CHROMA_B (REG_CHIPTOP_BASE + 0x3d*2)
253 #define REG_CKG_MVD_CHROMA_C (REG_CHIPTOP_BASE + 0x3d*2 + 1)
257 #define REG_CKG_MVD_LUMA_A (REG_CHIPTOP_BASE + 0x3a*2 + 1)
261 #define REG_CKG_MVD_LUMA_B (REG_CHIPTOP_BASE + 0x3b*2)
265 #define REG_CKG_MVD_LUMA_C (REG_CHIPTOP_BASE + 0x3b*2 + 1)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mainz/mvd_ex/
H A DregMVD_EX.h203 #define REG_CHIPTOP_BASE 0x0b00UL macro
205 #define REG_CKG_MVD_SYNC (REG_CHIPTOP_BASE + 0x38*2 +1)
208 #define REG_CKG_MVD (REG_CHIPTOP_BASE + 0x39*2)
221 #define REG_CKG_MVD2 (REG_CHIPTOP_BASE + 0x39*2 +1)
234 #define REG_CKG_MVD_CHROMA_A (REG_CHIPTOP_BASE + 0x3d*2)
238 #define REG_CKG_MVD_CHROMA_B (REG_CHIPTOP_BASE + 0x3d*2)
242 #define REG_CKG_MVD_CHROMA_C (REG_CHIPTOP_BASE + 0x3d*2 + 1)
246 #define REG_CKG_MVD_LUMA_A (REG_CHIPTOP_BASE + 0x3a*2 + 1)
250 #define REG_CKG_MVD_LUMA_B (REG_CHIPTOP_BASE + 0x3b*2)
254 #define REG_CKG_MVD_LUMA_C (REG_CHIPTOP_BASE + 0x3b*2 + 1)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/manhattan/mvd_ex/
H A DregMVD_EX.h203 #define REG_CHIPTOP_BASE 0x0b00UL macro
205 #define REG_CKG_MVD_SYNC (REG_CHIPTOP_BASE + 0x38*2 +1)
208 #define REG_CKG_MVD (REG_CHIPTOP_BASE + 0x39*2)
221 #define REG_CKG_MVD2 (REG_CHIPTOP_BASE + 0x39*2 +1)
234 #define REG_CKG_MVD_CHROMA_A (REG_CHIPTOP_BASE + 0x3d*2)
238 #define REG_CKG_MVD_CHROMA_B (REG_CHIPTOP_BASE + 0x3d*2)
242 #define REG_CKG_MVD_CHROMA_C (REG_CHIPTOP_BASE + 0x3d*2 + 1)
246 #define REG_CKG_MVD_LUMA_A (REG_CHIPTOP_BASE + 0x3a*2 + 1)
250 #define REG_CKG_MVD_LUMA_B (REG_CHIPTOP_BASE + 0x3b*2)
254 #define REG_CKG_MVD_LUMA_C (REG_CHIPTOP_BASE + 0x3b*2 + 1)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7621/mvd/
H A DregMVD.h214 #define REG_CHIPTOP_BASE 0x0b00 macro
216 #define REG_CKG_MVD_SYNC (REG_CHIPTOP_BASE + 0x38*2 +1)
219 #define REG_CKG_MVD (REG_CHIPTOP_BASE + 0x39*2)
232 #define REG_CKG_MVD2 (REG_CHIPTOP_BASE + 0x39*2 +1)
245 #define REG_CKG_MVD_CHROMA_A (REG_CHIPTOP_BASE + 0x3d*2)
249 #define REG_CKG_MVD_CHROMA_B (REG_CHIPTOP_BASE + 0x3d*2)
253 #define REG_CKG_MVD_CHROMA_C (REG_CHIPTOP_BASE + 0x3d*2 + 1)
257 #define REG_CKG_MVD_LUMA_A (REG_CHIPTOP_BASE + 0x3a*2 + 1)
261 #define REG_CKG_MVD_LUMA_B (REG_CHIPTOP_BASE + 0x3b*2)
265 #define REG_CKG_MVD_LUMA_C (REG_CHIPTOP_BASE + 0x3b*2 + 1)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7821/mvd/
H A DregMVD.h214 #define REG_CHIPTOP_BASE 0x0b00 macro
216 #define REG_CKG_MVD_SYNC (REG_CHIPTOP_BASE + 0x38*2 +1)
219 #define REG_CKG_MVD (REG_CHIPTOP_BASE + 0x39*2)
232 #define REG_CKG_MVD2 (REG_CHIPTOP_BASE + 0x39*2 +1)
245 #define REG_CKG_MVD_CHROMA_A (REG_CHIPTOP_BASE + 0x3d*2)
249 #define REG_CKG_MVD_CHROMA_B (REG_CHIPTOP_BASE + 0x3d*2)
253 #define REG_CKG_MVD_CHROMA_C (REG_CHIPTOP_BASE + 0x3d*2 + 1)
257 #define REG_CKG_MVD_LUMA_A (REG_CHIPTOP_BASE + 0x3a*2 + 1)
261 #define REG_CKG_MVD_LUMA_B (REG_CHIPTOP_BASE + 0x3b*2)
265 #define REG_CKG_MVD_LUMA_C (REG_CHIPTOP_BASE + 0x3b*2 + 1)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maldives/mvd_ex/
H A DregMVD_EX.h203 #define REG_CHIPTOP_BASE 0x0b00 macro
205 #define REG_CKG_MVD_SYNC (REG_CHIPTOP_BASE + 0x38*2 +1)
208 #define REG_CKG_MVD (REG_CHIPTOP_BASE + 0x39*2)
219 #define REG_CKG_MVD2 (REG_CHIPTOP_BASE + 0x39*2 +1)
229 #define REG_CKG_MVD_CHROMA_A (REG_CHIPTOP_BASE + 0x3d*2)
233 #define REG_CKG_MVD_CHROMA_B (REG_CHIPTOP_BASE + 0x3d*2)
237 #define REG_CKG_MVD_CHROMA_C (REG_CHIPTOP_BASE + 0x3d*2 + 1)
241 #define REG_CKG_MVD_LUMA_A (REG_CHIPTOP_BASE + 0x3a*2 + 1)
245 #define REG_CKG_MVD_LUMA_B (REG_CHIPTOP_BASE + 0x3b*2)
249 #define REG_CKG_MVD_LUMA_C (REG_CHIPTOP_BASE + 0x3b*2 + 1)
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/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/messi/mvd_ex/
H A DregMVD_EX.h203 #define REG_CHIPTOP_BASE 0x0b00UL macro
205 #define REG_CKG_MVD_SYNC (REG_CHIPTOP_BASE + 0x38*2 +1)
208 #define REG_CKG_MVD (REG_CHIPTOP_BASE + 0x39*2)
221 #define REG_CKG_MVD2 (REG_CHIPTOP_BASE + 0x39*2 +1)
234 #define REG_CKG_MVD_CHROMA_A (REG_CHIPTOP_BASE + 0x3d*2)
238 #define REG_CKG_MVD_CHROMA_B (REG_CHIPTOP_BASE + 0x3d*2)
242 #define REG_CKG_MVD_CHROMA_C (REG_CHIPTOP_BASE + 0x3d*2 + 1)
246 #define REG_CKG_MVD_LUMA_A (REG_CHIPTOP_BASE + 0x3a*2 + 1)
250 #define REG_CKG_MVD_LUMA_B (REG_CHIPTOP_BASE + 0x3b*2)
254 #define REG_CKG_MVD_LUMA_C (REG_CHIPTOP_BASE + 0x3b*2 + 1)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7821/mvd_ex/
H A DregMVD_EX.h203 #define REG_CHIPTOP_BASE 0x0b00UL macro
205 #define REG_CKG_MVD_SYNC (REG_CHIPTOP_BASE + 0x38*2 +1)
208 #define REG_CKG_MVD (REG_CHIPTOP_BASE + 0x39*2)
221 #define REG_CKG_MVD2 (REG_CHIPTOP_BASE + 0x39*2 +1)
234 #define REG_CKG_MVD_CHROMA_A (REG_CHIPTOP_BASE + 0x3d*2)
238 #define REG_CKG_MVD_CHROMA_B (REG_CHIPTOP_BASE + 0x3d*2)
242 #define REG_CKG_MVD_CHROMA_C (REG_CHIPTOP_BASE + 0x3d*2 + 1)
246 #define REG_CKG_MVD_LUMA_A (REG_CHIPTOP_BASE + 0x3a*2 + 1)
250 #define REG_CKG_MVD_LUMA_B (REG_CHIPTOP_BASE + 0x3b*2)
254 #define REG_CKG_MVD_LUMA_C (REG_CHIPTOP_BASE + 0x3b*2 + 1)
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