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Searched refs:REG_BW_ADDR_SIZE (Results 1 – 25 of 25) sorted by relevance

/utopia/UTPA2-700.0.x/modules/pq/hal/maxim/pq/include/
H A DQualityMap_BW.c100 #define REG_BW_ADDR_SIZE 3 macro
136 …u8Value = ptab_Info->pIPTable[REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+ptab_Info->u8TabI… in _MDrv_BW_DumpTable()
173 …ptab_Info->pIPTable+=(REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+ptab_Info->u8TabNums); //… in _MDrv_BW_DumpTable()
H A DManhattan_Bandwidth_RegTable.c21 code U8 BWTABLE_COM[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+1] =
168 code U8 BWTABLE[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+BWTABLE_NUMS]=
H A DMaserati_Bandwidth_RegTable.c21 code U8 BWTABLE_COM[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+1] =
245 code U8 BWTABLE[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+BWTABLE_NUMS]=
/utopia/UTPA2-700.0.x/modules/pq/hal/curry/pq/include/
H A DQualityMap_BW.c101 #define REG_BW_ADDR_SIZE 3 macro
137 …u8Value = ptab_Info->pIPTable[REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+ptab_Info->u8TabI… in _MDrv_BW_DumpTable()
169 …ptab_Info->pIPTable+=(REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+ptab_Info->u8TabNums); //… in _MDrv_BW_DumpTable()
H A DCurry_Bandwidth_RegTable.c21 code U8 BWTABLE_COM[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+1] =
160 code U8 BWTABLE[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+BWTABLE_NUMS]=
H A DKano_Bandwidth_RegTable.c21 code U8 BWTABLE_COM[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+1] =
160 code U8 BWTABLE[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+BWTABLE_NUMS]=
/utopia/UTPA2-700.0.x/modules/pq/hal/maserati/pq/include/
H A DQualityMap_BW.c100 #define REG_BW_ADDR_SIZE 3 macro
136 …u8Value = ptab_Info->pIPTable[REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+ptab_Info->u8TabI… in _MDrv_BW_DumpTable()
173 …ptab_Info->pIPTable+=(REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+ptab_Info->u8TabNums); //… in _MDrv_BW_DumpTable()
H A DManhattan_Bandwidth_RegTable.c21 code U8 BWTABLE_COM[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+1] =
168 code U8 BWTABLE[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+BWTABLE_NUMS]=
H A DMaserati_Bandwidth_RegTable.c21 code U8 BWTABLE_COM[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+1] =
247 code U8 BWTABLE[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+BWTABLE_NUMS]=
/utopia/UTPA2-700.0.x/modules/pq/hal/M7821/pq/include/
H A DQualityMap_BW.c100 #define REG_BW_ADDR_SIZE 3 macro
136 …u8Value = ptab_Info->pIPTable[REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+ptab_Info->u8TabI… in _MDrv_BW_DumpTable()
173 …ptab_Info->pIPTable+=(REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+ptab_Info->u8TabNums); //… in _MDrv_BW_DumpTable()
H A DManhattan_Bandwidth_RegTable.c21 code U8 BWTABLE_COM[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+1] =
168 code U8 BWTABLE[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+BWTABLE_NUMS]=
H A DMaserati_Bandwidth_RegTable.c21 code U8 BWTABLE_COM[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+1] =
245 code U8 BWTABLE[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+BWTABLE_NUMS]=
/utopia/UTPA2-700.0.x/modules/pq/hal/kano/pq/include/
H A DQualityMap_BW.c101 #define REG_BW_ADDR_SIZE 3 macro
137 …u8Value = ptab_Info->pIPTable[REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+ptab_Info->u8TabI… in _MDrv_BW_DumpTable()
169 …ptab_Info->pIPTable+=(REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+ptab_Info->u8TabNums); //… in _MDrv_BW_DumpTable()
H A DKano_Bandwidth_RegTable.c21 code U8 BWTABLE_COM[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+1] =
160 code U8 BWTABLE[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+BWTABLE_NUMS]=
/utopia/UTPA2-700.0.x/modules/pq/hal/mooney/pq/include/
H A DQualityMap_BW.c101 #define REG_BW_ADDR_SIZE 3 macro
137 …u8Value = ptab_Info->pIPTable[REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+ptab_Info->u8TabI… in _MDrv_BW_DumpTable()
170 …ptab_Info->pIPTable+=(REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+ptab_Info->u8TabNums); //… in _MDrv_BW_DumpTable()
H A DMooney_Bandwidth_RegTable.c21 code U8 BWTABLE_COM[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+1] =
170 code U8 BWTABLE[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+BWTABLE_NUMS]=
/utopia/UTPA2-700.0.x/modules/pq/hal/manhattan/pq/include/
H A DQualityMap_BW.c100 #define REG_BW_ADDR_SIZE 3 macro
136 …u8Value = ptab_Info->pIPTable[REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+ptab_Info->u8TabI… in _MDrv_BW_DumpTable()
173 …ptab_Info->pIPTable+=(REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+ptab_Info->u8TabNums); //… in _MDrv_BW_DumpTable()
H A DManhattan_Bandwidth_RegTable.c21 code U8 BWTABLE_COM[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+1] =
168 code U8 BWTABLE[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+BWTABLE_NUMS]=
/utopia/UTPA2-700.0.x/modules/pq/hal/M7621/pq/include/
H A DQualityMap_BW.c100 #define REG_BW_ADDR_SIZE 3 macro
136 …u8Value = ptab_Info->pIPTable[REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+ptab_Info->u8TabI… in _MDrv_BW_DumpTable()
173 …ptab_Info->pIPTable+=(REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+ptab_Info->u8TabNums); //… in _MDrv_BW_DumpTable()
H A DManhattan_Bandwidth_RegTable.c21 code U8 BWTABLE_COM[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+1] =
168 code U8 BWTABLE[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+BWTABLE_NUMS]=
H A DMaserati_Bandwidth_RegTable.c21 code U8 BWTABLE_COM[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+1] =
245 code U8 BWTABLE[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+BWTABLE_NUMS]=
/utopia/UTPA2-700.0.x/modules/pq/hal/k6lite/pq/include/
H A DQualityMap_BW.c101 #define REG_BW_ADDR_SIZE 3 macro
137 …u8Value = ptab_Info->pIPTable[REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+ptab_Info->u8TabI… in _MDrv_BW_DumpTable()
169 …ptab_Info->pIPTable+=(REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+ptab_Info->u8TabNums); //… in _MDrv_BW_DumpTable()
H A Dk6lite_Bandwidth_RegTable.c21 code U8 BWTABLE_COM[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+1] =
167 code U8 BWTABLE[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+BWTABLE_NUMS]=
/utopia/UTPA2-700.0.x/modules/pq/hal/k6/pq/include/
H A DQualityMap_BW.c101 #define REG_BW_ADDR_SIZE 3 macro
137 …u8Value = ptab_Info->pIPTable[REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+ptab_Info->u8TabI… in _MDrv_BW_DumpTable()
169 …ptab_Info->pIPTable+=(REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+ptab_Info->u8TabNums); //… in _MDrv_BW_DumpTable()
H A Dk6_Bandwidth_RegTable.c21 code U8 BWTABLE_COM[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+1] =
161 code U8 BWTABLE[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+BWTABLE_NUMS]=