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Searched refs:REG_ADC_DTOP_19_H (Results 1 – 25 of 41) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_adctbl.c62 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x1E, 0x00, 0x04/*$All*/, },
1989 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x60, 0x00, 0x40/*ADC_TABLE_FREQ_SECTION1*/,
2266 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x60, 0x00, 0x40/*ADC_TABLE_FREQ_SECTION1*/,
H A Dhwreg_adc_dtop.h157 #define REG_ADC_DTOP_19_H (REG_ADC_DTOP_BASE + 0x33) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dmhal_adctbl.c62 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x1E, 0x00, 0x04/*$All*/, },
1989 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x60, 0x00, 0x40/*ADC_TABLE_FREQ_SECTION1*/,
2266 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x60, 0x00, 0x40/*ADC_TABLE_FREQ_SECTION1*/,
H A Dhwreg_adc_dtop.h157 #define REG_ADC_DTOP_19_H (REG_ADC_DTOP_BASE + 0x33) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dmhal_adctbl.c62 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x1E, 0x00, 0x04/*$All*/, },
1989 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x60, 0x00, 0x40/*ADC_TABLE_FREQ_SECTION1*/,
2266 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x60, 0x00, 0x40/*ADC_TABLE_FREQ_SECTION1*/,
H A Dhwreg_adc_dtop.h157 #define REG_ADC_DTOP_19_H (REG_ADC_DTOP_BASE + 0x33) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_adctbl.c62 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x1E, 0x00, 0x04/*$All*/, },
1940 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x60, 0x00, 0x40/*ADC_TABLE_FREQ_SECTION1*/,
2217 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x60, 0x00, 0x40/*ADC_TABLE_FREQ_SECTION1*/,
H A Dhwreg_adc_dtop.h157 #define REG_ADC_DTOP_19_H (REG_ADC_DTOP_BASE + 0x33) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_adctbl.c62 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x1E, 0x00, 0x04/*$All*/, },
2043 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x60, 0x00, 0x40/*ADC_TABLE_FREQ_SECTION1*/,
2320 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x60, 0x00, 0x40/*ADC_TABLE_FREQ_SECTION1*/,
H A Dhwreg_adc_dtop.h157 #define REG_ADC_DTOP_19_H (REG_ADC_DTOP_BASE + 0x33) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_adctbl.c62 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x1E, 0x00, 0x04/*$All*/, },
2043 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x60, 0x00, 0x40/*ADC_TABLE_FREQ_SECTION1*/,
2320 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x60, 0x00, 0x40/*ADC_TABLE_FREQ_SECTION1*/,
H A Dhwreg_adc_dtop.h157 #define REG_ADC_DTOP_19_H (REG_ADC_DTOP_BASE + 0x33) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_adctbl.c62 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x1E, 0x00, 0x04/*$All*/, },
2043 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x60, 0x00, 0x40/*ADC_TABLE_FREQ_SECTION1*/,
2320 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x60, 0x00, 0x40/*ADC_TABLE_FREQ_SECTION1*/,
H A Dhwreg_adc_dtop.h157 #define REG_ADC_DTOP_19_H (REG_ADC_DTOP_BASE + 0x33) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dmhal_adctbl.c62 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x1E, 0x00, 0x04/*$All*/, },
2092 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x60, 0x00, 0x40/*ADC_TABLE_FREQ_SECTION1*/,
2369 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x60, 0x00, 0x40/*ADC_TABLE_FREQ_SECTION1*/,
H A Dhwreg_adc_dtop.h157 #define REG_ADC_DTOP_19_H (REG_ADC_DTOP_BASE + 0x33) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_adctbl.c62 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x1E, 0x00, 0x04/*$All*/, },
2043 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x60, 0x00, 0x40/*ADC_TABLE_FREQ_SECTION1*/,
2320 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x60, 0x00, 0x40/*ADC_TABLE_FREQ_SECTION1*/,
H A Dhwreg_adc_dtop.h157 #define REG_ADC_DTOP_19_H (REG_ADC_DTOP_BASE + 0x33) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_adctbl.c62 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x1E, 0x00, 0x04/*$All*/, },
2043 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x60, 0x00, 0x40/*ADC_TABLE_FREQ_SECTION1*/,
2320 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x60, 0x00, 0x40/*ADC_TABLE_FREQ_SECTION1*/,
H A Dhwreg_adc_dtop.h157 #define REG_ADC_DTOP_19_H (REG_ADC_DTOP_BASE + 0x33) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dmhal_adctbl.c62 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x1E, 0x00, 0x04/*$All*/, },
2092 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x60, 0x00, 0x40/*ADC_TABLE_FREQ_SECTION1*/,
2369 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x60, 0x00, 0x40/*ADC_TABLE_FREQ_SECTION1*/,
H A Dhwreg_adc_dtop.h157 #define REG_ADC_DTOP_19_H (REG_ADC_DTOP_BASE + 0x33) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_adc_dtop.h157 #define REG_ADC_DTOP_19_H (REG_ADC_DTOP_BASE + 0x33) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_adc_dtop.h157 #define REG_ADC_DTOP_19_H (REG_ADC_DTOP_BASE + 0x33) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_adc_dtop.h157 #define REG_ADC_DTOP_19_H (REG_ADC_DTOP_BASE + 0x33) macro

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