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Searched refs:REG_ADC_DTOPB_53_H (Results 1 – 22 of 22) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_adctbl.c1721 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x18, 0x00, 0x08/*ALL*/, },
1729 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
1743 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x18, 0x00, 0x10/*ALL*/, },
1744 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x20, 0x00, 0x20/*ALL*/, },
1755 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
H A Dhwreg_adc_dtopb.h273 #define REG_ADC_DTOPB_53_H (REG_ADC_DTOPB_BASE + 0xA7) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dmhal_adctbl.c1721 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x18, 0x00, 0x08/*ALL*/, },
1729 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
1743 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x18, 0x00, 0x10/*ALL*/, },
1744 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x20, 0x00, 0x20/*ALL*/, },
1755 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
H A Dhwreg_adc_dtopb.h273 #define REG_ADC_DTOPB_53_H (REG_ADC_DTOPB_BASE + 0xA7) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dmhal_adctbl.c1721 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x18, 0x00, 0x08/*ALL*/, },
1729 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
1743 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x18, 0x00, 0x10/*ALL*/, },
1744 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x20, 0x00, 0x20/*ALL*/, },
1755 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
H A Dhwreg_adc_dtopb.h273 #define REG_ADC_DTOPB_53_H (REG_ADC_DTOPB_BASE + 0xA7) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_adctbl.c1672 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x18, 0x00, 0x08/*ALL*/, },
1680 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
1694 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x18, 0x00, 0x10/*ALL*/, },
1695 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x20, 0x00, 0x20/*ALL*/, },
1706 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
H A Dhwreg_adc_dtopb.h273 #define REG_ADC_DTOPB_53_H (REG_ADC_DTOPB_BASE + 0xA7) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_adctbl.c1737 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x18, 0x00, 0x08/*ALL*/, },
1745 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
1759 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x18, 0x00, 0x10/*ALL*/, },
1760 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x20, 0x00, 0x20/*ALL*/, },
1771 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
H A Dhwreg_adc_dtopb.h273 #define REG_ADC_DTOPB_53_H (REG_ADC_DTOPB_BASE + 0xA7) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_adctbl.c1737 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x18, 0x00, 0x08/*ALL*/, },
1745 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
1759 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x18, 0x00, 0x10/*ALL*/, },
1760 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x20, 0x00, 0x20/*ALL*/, },
1771 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
H A Dhwreg_adc_dtopb.h273 #define REG_ADC_DTOPB_53_H (REG_ADC_DTOPB_BASE + 0xA7) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_adctbl.c1737 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x18, 0x00, 0x08/*ALL*/, },
1745 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
1759 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x18, 0x00, 0x10/*ALL*/, },
1760 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x20, 0x00, 0x20/*ALL*/, },
1771 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
H A Dhwreg_adc_dtopb.h273 #define REG_ADC_DTOPB_53_H (REG_ADC_DTOPB_BASE + 0xA7) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dmhal_adctbl.c1786 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x18, 0x00, 0x08/*ALL*/, },
1794 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
1808 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x18, 0x00, 0x10/*ALL*/, },
1809 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x20, 0x00, 0x20/*ALL*/, },
1820 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
H A Dhwreg_adc_dtopb.h273 #define REG_ADC_DTOPB_53_H (REG_ADC_DTOPB_BASE + 0xA7) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_adctbl.c1737 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x18, 0x00, 0x08/*ALL*/, },
1745 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
1759 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x18, 0x00, 0x10/*ALL*/, },
1760 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x20, 0x00, 0x20/*ALL*/, },
1771 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
H A Dhwreg_adc_dtopb.h273 #define REG_ADC_DTOPB_53_H (REG_ADC_DTOPB_BASE + 0xA7) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_adctbl.c1737 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x18, 0x00, 0x08/*ALL*/, },
1745 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
1759 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x18, 0x00, 0x10/*ALL*/, },
1760 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x20, 0x00, 0x20/*ALL*/, },
1771 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
H A Dhwreg_adc_dtopb.h273 #define REG_ADC_DTOPB_53_H (REG_ADC_DTOPB_BASE + 0xA7) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dmhal_adctbl.c1786 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x18, 0x00, 0x08/*ALL*/, },
1794 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
1808 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x18, 0x00, 0x10/*ALL*/, },
1809 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x20, 0x00, 0x20/*ALL*/, },
1820 { DRV_ADC_REG(REG_ADC_DTOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
H A Dhwreg_adc_dtopb.h273 #define REG_ADC_DTOPB_53_H (REG_ADC_DTOPB_BASE + 0xA7) macro