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Searched refs:PQ_HSPRule_IP_NUM_Sub (Results 1 – 21 of 21) sorted by relevance

/utopia/UTPA2-700.0.x/modules/pq/hal/M7821/pq/include/
H A DMaserati_Sub_HSPRule.h2 #define PQ_HSPRule_IP_NUM_Sub 3 macro
34 extern code U8 MST_HSPRule_IP_Index_Sub[PQ_HSPRule_IP_NUM_Sub];
35 extern code U8 MST_HSPRule_Array_Sub[PQ_HSPRule_NUM_Sub][PQ_HSPRule_IP_NUM_Sub];
H A DMaserati_Sub_HSPRule.c2 code U8 MST_HSPRule_IP_Index_Sub[PQ_HSPRule_IP_NUM_Sub]=
10 code U8 MST_HSPRule_Array_Sub[PQ_HSPRule_NUM_Sub][PQ_HSPRule_IP_NUM_Sub]=
/utopia/UTPA2-700.0.x/modules/pq/hal/M7621/pq/include/
H A DMaxim_Sub_HSPRule.h2 #define PQ_HSPRule_IP_NUM_Sub 3 macro
34 extern code U8 MST_HSPRule_IP_Index_Sub[PQ_HSPRule_IP_NUM_Sub];
35 extern code U8 MST_HSPRule_Array_Sub[PQ_HSPRule_NUM_Sub][PQ_HSPRule_IP_NUM_Sub];
H A DMaxim_Sub_HSPRule.c2 code U8 MST_HSPRule_IP_Index_Sub[PQ_HSPRule_IP_NUM_Sub]=
10 code U8 MST_HSPRule_Array_Sub[PQ_HSPRule_NUM_Sub][PQ_HSPRule_IP_NUM_Sub]=
/utopia/UTPA2-700.0.x/modules/pq/hal/maserati/pq/include/
H A DMaserati_Sub_HSPRule.h2 #define PQ_HSPRule_IP_NUM_Sub 3 macro
34 extern code U8 MST_HSPRule_IP_Index_Sub[PQ_HSPRule_IP_NUM_Sub];
35 extern code U8 MST_HSPRule_Array_Sub[PQ_HSPRule_NUM_Sub][PQ_HSPRule_IP_NUM_Sub];
H A DMaserati_Sub_HSPRule.c2 code U8 MST_HSPRule_IP_Index_Sub[PQ_HSPRule_IP_NUM_Sub]=
10 code U8 MST_HSPRule_Array_Sub[PQ_HSPRule_NUM_Sub][PQ_HSPRule_IP_NUM_Sub]=
/utopia/UTPA2-700.0.x/modules/pq/hal/maxim/pq/include/
H A DMaxim_Sub_HSPRule.h2 #define PQ_HSPRule_IP_NUM_Sub 3 macro
34 extern code U8 MST_HSPRule_IP_Index_Sub[PQ_HSPRule_IP_NUM_Sub];
35 extern code U8 MST_HSPRule_Array_Sub[PQ_HSPRule_NUM_Sub][PQ_HSPRule_IP_NUM_Sub];
H A DMaxim_Sub_HSPRule.c2 code U8 MST_HSPRule_IP_Index_Sub[PQ_HSPRule_IP_NUM_Sub]=
10 code U8 MST_HSPRule_Array_Sub[PQ_HSPRule_NUM_Sub][PQ_HSPRule_IP_NUM_Sub]=
/utopia/UTPA2-700.0.x/modules/pq/hal/manhattan/pq/include/
H A DManhattan_Sub_HSPRule.h2 #define PQ_HSPRule_IP_NUM_Sub 3 macro
34 extern code U8 MST_HSPRule_IP_Index_Sub[PQ_HSPRule_IP_NUM_Sub];
35 extern code U8 MST_HSPRule_Array_Sub[PQ_HSPRule_NUM_Sub][PQ_HSPRule_IP_NUM_Sub];
H A DManhattan_Sub_HSPRule.c2 code U8 MST_HSPRule_IP_Index_Sub[PQ_HSPRule_IP_NUM_Sub]=
10 code U8 MST_HSPRule_Array_Sub[PQ_HSPRule_NUM_Sub][PQ_HSPRule_IP_NUM_Sub]=
/utopia/UTPA2-700.0.x/modules/pq/hal/kano/pq/include/
H A DKano_Sub_HSPRule.h2 #define PQ_HSPRule_IP_NUM_Sub 4 macro
34 extern code U8 MST_HSPRule_IP_Index_Sub[PQ_HSPRule_IP_NUM_Sub];
35 extern code U8 MST_HSPRule_Array_Sub[PQ_HSPRule_NUM_Sub][PQ_HSPRule_IP_NUM_Sub];
H A DKano_Sub_HSPRule.c2 code U8 MST_HSPRule_IP_Index_Sub[PQ_HSPRule_IP_NUM_Sub]=
11 code U8 MST_HSPRule_Array_Sub[PQ_HSPRule_NUM_Sub][PQ_HSPRule_IP_NUM_Sub]=
/utopia/UTPA2-700.0.x/modules/pq/hal/curry/pq/include/
H A DCurry_Sub_HSPRule.h2 #define PQ_HSPRule_IP_NUM_Sub 4 macro
34 extern code U8 MST_HSPRule_IP_Index_Sub[PQ_HSPRule_IP_NUM_Sub];
35 extern code U8 MST_HSPRule_Array_Sub[PQ_HSPRule_NUM_Sub][PQ_HSPRule_IP_NUM_Sub];
H A DKano_Sub_HSPRule.h2 #define PQ_HSPRule_IP_NUM_Sub 4 macro
34 extern code U8 MST_HSPRule_IP_Index_Sub[PQ_HSPRule_IP_NUM_Sub];
35 extern code U8 MST_HSPRule_Array_Sub[PQ_HSPRule_NUM_Sub][PQ_HSPRule_IP_NUM_Sub];
H A DCurry_Sub_HSPRule.c2 code U8 MST_HSPRule_IP_Index_Sub[PQ_HSPRule_IP_NUM_Sub]=
11 code U8 MST_HSPRule_Array_Sub[PQ_HSPRule_NUM_Sub][PQ_HSPRule_IP_NUM_Sub]=
H A DKano_Sub_HSPRule.c2 code U8 MST_HSPRule_IP_Index_Sub[PQ_HSPRule_IP_NUM_Sub]=
11 code U8 MST_HSPRule_Array_Sub[PQ_HSPRule_NUM_Sub][PQ_HSPRule_IP_NUM_Sub]=
/utopia/UTPA2-700.0.x/modules/pq/hal/k6lite/pq/include/
H A Dk6lite_Sub_HSPRule.h2 #define PQ_HSPRule_IP_NUM_Sub 4 macro
34 extern code U8 MST_HSPRule_IP_Index_Sub[PQ_HSPRule_IP_NUM_Sub];
35 extern code U8 MST_HSPRule_Array_Sub[PQ_HSPRule_NUM_Sub][PQ_HSPRule_IP_NUM_Sub];
H A Dk6lite_Sub_HSPRule.c2 code U8 MST_HSPRule_IP_Index_Sub[PQ_HSPRule_IP_NUM_Sub]=
11 code U8 MST_HSPRule_Array_Sub[PQ_HSPRule_NUM_Sub][PQ_HSPRule_IP_NUM_Sub]=
/utopia/UTPA2-700.0.x/modules/pq/hal/k6/pq/include/
H A Dk6_Sub_HSPRule.h2 #define PQ_HSPRule_IP_NUM_Sub 4 macro
34 extern code U8 MST_HSPRule_IP_Index_Sub[PQ_HSPRule_IP_NUM_Sub];
35 extern code U8 MST_HSPRule_Array_Sub[PQ_HSPRule_NUM_Sub][PQ_HSPRule_IP_NUM_Sub];
H A Dk6_Sub_HSPRule.c2 code U8 MST_HSPRule_IP_Index_Sub[PQ_HSPRule_IP_NUM_Sub]=
11 code U8 MST_HSPRule_Array_Sub[PQ_HSPRule_NUM_Sub][PQ_HSPRule_IP_NUM_Sub]=
/utopia/UTPA2-700.0.x/modules/pq/drv/pq/
H A DdrvPQ_cus.c3504 PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_HSP] = PQ_HSPRule_IP_NUM_Sub; in _MDrv_PQ_Set_DisplayType_Sub()