Searched refs:MULTI_CH_INPUT_DELAY_STORE_CHANNELS (Results 1 – 9 of 9) sorted by relevance
120 …#define MULTI_CH_INPUT_DELAY_STORE_CHANNELS 6 // multi-channel input delay function … macro139 …_INPUT_DLY_UPPER_BOUND ((MULTI_CH_INPUT_DLY_DRAM_SIZE/MULTI_CH_INPUT_DELAY_STORE_CHANNELS)/DM…890 …INPUT_DELAY_FIFO_SIZE = (SE_PROCESS_FIFO_SIZE_UNIT * MULTI_CH_INPUT_DELAY_STORE_CHANNELS); /…891 …NPUT_DELAY_DMA_WORDSIZE = (SE_PROCESS_DMA_WORD_SIZE_UNIT * MULTI_CH_INPUT_DELAY_STORE_CHANNELS);
127 …#define MULTI_CH_INPUT_DELAY_STORE_CHANNELS 6 // multi-channel input delay function … macro146 …_INPUT_DLY_UPPER_BOUND ((MULTI_CH_INPUT_DLY_DRAM_SIZE/MULTI_CH_INPUT_DELAY_STORE_CHANNELS)/DM…920 …INPUT_DELAY_FIFO_SIZE = (SE_PROCESS_FIFO_SIZE_UNIT * MULTI_CH_INPUT_DELAY_STORE_CHANNELS); /…921 …NPUT_DELAY_DMA_WORDSIZE = (SE_PROCESS_DMA_WORD_SIZE_UNIT * MULTI_CH_INPUT_DELAY_STORE_CHANNELS);
130 …#define MULTI_CH_INPUT_DELAY_STORE_CHANNELS 6 // multi-channel input delay function … macro146 …_INPUT_DLY_UPPER_BOUND ((MULTI_CH_INPUT_DLY_DRAM_SIZE/MULTI_CH_INPUT_DELAY_STORE_CHANNELS)/DM…1053 …INPUT_DELAY_FIFO_SIZE = (SE_PROCESS_FIFO_SIZE_UNIT * MULTI_CH_INPUT_DELAY_STORE_CHANNELS); /…1054 …NPUT_DELAY_DMA_WORDSIZE = (SE_PROCESS_DMA_WORD_SIZE_UNIT * MULTI_CH_INPUT_DELAY_STORE_CHANNELS);
128 …#define MULTI_CH_INPUT_DELAY_STORE_CHANNELS 6 // multi-channel input delay function … macro147 …_INPUT_DLY_UPPER_BOUND ((MULTI_CH_INPUT_DLY_DRAM_SIZE/MULTI_CH_INPUT_DELAY_STORE_CHANNELS)/DM…964 …INPUT_DELAY_FIFO_SIZE = (SE_PROCESS_FIFO_SIZE_UNIT * MULTI_CH_INPUT_DELAY_STORE_CHANNELS); /…965 …NPUT_DELAY_DMA_WORDSIZE = (SE_PROCESS_DMA_WORD_SIZE_UNIT * MULTI_CH_INPUT_DELAY_STORE_CHANNELS);
130 …#define MULTI_CH_INPUT_DELAY_STORE_CHANNELS 6 // multi-channel input delay function … macro146 …_INPUT_DLY_UPPER_BOUND ((MULTI_CH_INPUT_DLY_DRAM_SIZE/MULTI_CH_INPUT_DELAY_STORE_CHANNELS)/DM…1085 …INPUT_DELAY_FIFO_SIZE = (SE_PROCESS_FIFO_SIZE_UNIT * MULTI_CH_INPUT_DELAY_STORE_CHANNELS); /…1086 …NPUT_DELAY_DMA_WORDSIZE = (SE_PROCESS_DMA_WORD_SIZE_UNIT * MULTI_CH_INPUT_DELAY_STORE_CHANNELS);
130 …#define MULTI_CH_INPUT_DELAY_STORE_CHANNELS 6 // multi-channel input delay function … macro146 …_INPUT_DLY_UPPER_BOUND ((MULTI_CH_INPUT_DLY_DRAM_SIZE/MULTI_CH_INPUT_DELAY_STORE_CHANNELS)/DM…1067 …INPUT_DELAY_FIFO_SIZE = (SE_PROCESS_FIFO_SIZE_UNIT * MULTI_CH_INPUT_DELAY_STORE_CHANNELS); /…1068 …NPUT_DELAY_DMA_WORDSIZE = (SE_PROCESS_DMA_WORD_SIZE_UNIT * MULTI_CH_INPUT_DELAY_STORE_CHANNELS);
130 …#define MULTI_CH_INPUT_DELAY_STORE_CHANNELS 6 // multi-channel input delay function … macro146 …_INPUT_DLY_UPPER_BOUND ((MULTI_CH_INPUT_DLY_DRAM_SIZE/MULTI_CH_INPUT_DELAY_STORE_CHANNELS)/DM…1076 …INPUT_DELAY_FIFO_SIZE = (SE_PROCESS_FIFO_SIZE_UNIT * MULTI_CH_INPUT_DELAY_STORE_CHANNELS); /…1077 …NPUT_DELAY_DMA_WORDSIZE = (SE_PROCESS_DMA_WORD_SIZE_UNIT * MULTI_CH_INPUT_DELAY_STORE_CHANNELS);
137 …#define MULTI_CH_INPUT_DELAY_STORE_CHANNELS 6 // multi-channel input delay function … macro153 …_INPUT_DLY_UPPER_BOUND ((MULTI_CH_INPUT_DLY_DRAM_SIZE/MULTI_CH_INPUT_DELAY_STORE_CHANNELS)/DM…1128 …INPUT_DELAY_FIFO_SIZE = (SE_PROCESS_FIFO_SIZE_UNIT * MULTI_CH_INPUT_DELAY_STORE_CHANNELS); /…1129 …NPUT_DELAY_DMA_WORDSIZE = (SE_PROCESS_DMA_WORD_SIZE_UNIT * MULTI_CH_INPUT_DELAY_STORE_CHANNELS);
130 …#define MULTI_CH_INPUT_DELAY_STORE_CHANNELS 6 // multi-channel input delay function … macro146 …_INPUT_DLY_UPPER_BOUND ((MULTI_CH_INPUT_DLY_DRAM_SIZE/MULTI_CH_INPUT_DELAY_STORE_CHANNELS)/DM…1073 …INPUT_DELAY_FIFO_SIZE = (SE_PROCESS_FIFO_SIZE_UNIT * MULTI_CH_INPUT_DELAY_STORE_CHANNELS); /…1074 …NPUT_DELAY_DMA_WORDSIZE = (SE_PROCESS_DMA_WORD_SIZE_UNIT * MULTI_CH_INPUT_DELAY_STORE_CHANNELS);