Home
last modified time | relevance | path

Searched refs:MHL_PHASE_CODE_VALUE (Results 1 – 4 of 4) sorted by relevance

/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/mhl/internal/
H A DhalMHL.c530 W2BYTEMSK(REG_DVI_DTOP_3A_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
532 W2BYTEMSK(REG_DVI_DTOP_3C_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
534 W2BYTEMSK(REG_DVI_DTOP_3E_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
559 W2BYTEMSK(REG_DVI_DTOP1_3A_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
561 W2BYTEMSK(REG_DVI_DTOP1_3C_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
563 W2BYTEMSK(REG_DVI_DTOP1_3E_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
587 W2BYTEMSK(REG_DVI_DTOP3_3A_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
589 W2BYTEMSK(REG_DVI_DTOP3_3C_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
591 W2BYTEMSK(REG_DVI_DTOP3_3E_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
616 W2BYTEMSK(REG_DVI_DTOP2_3A_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
[all …]
H A DhalMHL.h103 #define MHL_PHASE_CODE_VALUE 0x60 macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/mhl/internal/
H A DhalMHL.c530 W2BYTEMSK(REG_DVI_DTOP_3A_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
532 W2BYTEMSK(REG_DVI_DTOP_3C_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
534 W2BYTEMSK(REG_DVI_DTOP_3E_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
559 W2BYTEMSK(REG_DVI_DTOP1_3A_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
561 W2BYTEMSK(REG_DVI_DTOP1_3C_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
563 W2BYTEMSK(REG_DVI_DTOP1_3E_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
587 W2BYTEMSK(REG_DVI_DTOP3_3A_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
589 W2BYTEMSK(REG_DVI_DTOP3_3C_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
591 W2BYTEMSK(REG_DVI_DTOP3_3E_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
616 W2BYTEMSK(REG_DVI_DTOP2_3A_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A in _mhal_mhl_Mhl24bitsModeSetting()
[all …]
H A DhalMHL.h103 #define MHL_PHASE_CODE_VALUE 0x60 macro