| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/ |
| H A D | Maserati_2D_4K2K.c | 9 MDrv_WriteByteMask( REG_FSC_BK20_A2, 0x80, 0xff); // reg_splt_gb_in_size_r in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
10 MDrv_WriteByteMask( REG_FSC_BK20_A3, 0x00, 0x01); // reg_splt_gb_in_size_r in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
11 MDrv_WriteByteMask( REG_FSC_BK20_A4, 0x80, 0xff); // reg_splt_h_size in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
12 MDrv_WriteByteMask( REG_FSC_BK20_A5, 0x07, 0x1f); // reg_splt_h_size in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
13 MDrv_WriteByteMask( REG_FSC_BK20_A6, 0xc0, 0xff); // reg_splt_h_size_l in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
14 MDrv_WriteByteMask( REG_FSC_BK20_A7, 0x03, 0x0f); // reg_splt_h_size_l in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
15 MDrv_WriteByteMask( REG_FSC_BK20_A8, 0x80, 0x80); // reg_mcm_lr_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
16 MDrv_WriteByteMask( REG_FSC_BK20_49, 0x04, 0x0f); // reg_vertical_limit_cnt in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
17 MDrv_WriteByteMask( REG_FSC_BK20_48, 0x38, 0xff); // reg_vertical_limit_cnt in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
18 MDrv_WriteByteMask( REG_FSC_BK20_1D, 0x00, 0x1f); // reg_hde_st in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
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| H A D | Maserati_2D_480.c | 9 MDrv_WriteByteMask( REG_FSC_BK20_A2, 0x80, 0xff); // reg_splt_gb_in_size_r in MFC_3D_2D_480_2D_480_RGB_BYPASS()
10 MDrv_WriteByteMask( REG_FSC_BK20_A3, 0x00, 0x01); // reg_splt_gb_in_size_r in MFC_3D_2D_480_2D_480_RGB_BYPASS()
11 MDrv_WriteByteMask( REG_FSC_BK20_A4, 0x80, 0xff); // reg_splt_h_size in MFC_3D_2D_480_2D_480_RGB_BYPASS()
12 MDrv_WriteByteMask( REG_FSC_BK20_A5, 0x07, 0x1f); // reg_splt_h_size in MFC_3D_2D_480_2D_480_RGB_BYPASS()
13 MDrv_WriteByteMask( REG_FSC_BK20_A6, 0xc0, 0xff); // reg_splt_h_size_l in MFC_3D_2D_480_2D_480_RGB_BYPASS()
14 MDrv_WriteByteMask( REG_FSC_BK20_A7, 0x03, 0x0f); // reg_splt_h_size_l in MFC_3D_2D_480_2D_480_RGB_BYPASS()
15 MDrv_WriteByteMask( REG_FSC_BK20_A8, 0x80, 0x80); // reg_mcm_lr_en in MFC_3D_2D_480_2D_480_RGB_BYPASS()
16 MDrv_WriteByteMask( REG_FSC_BK20_49, 0x04, 0x0f); // reg_vertical_limit_cnt in MFC_3D_2D_480_2D_480_RGB_BYPASS()
17 MDrv_WriteByteMask( REG_FSC_BK20_48, 0x38, 0xff); // reg_vertical_limit_cnt in MFC_3D_2D_480_2D_480_RGB_BYPASS()
18 MDrv_WriteByteMask( REG_FSC_BK20_1D, 0x00, 0x1f); // reg_hde_st in MFC_3D_2D_480_2D_480_RGB_BYPASS()
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| H A D | Maserati_2D_576.c | 9 MDrv_WriteByteMask( REG_FSC_BK20_A2, 0x80, 0xff); // reg_splt_gb_in_size_r in MFC_3D_2D_576_2D_576_RGB_BYPASS()
10 MDrv_WriteByteMask( REG_FSC_BK20_A3, 0x00, 0x01); // reg_splt_gb_in_size_r in MFC_3D_2D_576_2D_576_RGB_BYPASS()
11 MDrv_WriteByteMask( REG_FSC_BK20_A4, 0x80, 0xff); // reg_splt_h_size in MFC_3D_2D_576_2D_576_RGB_BYPASS()
12 MDrv_WriteByteMask( REG_FSC_BK20_A5, 0x07, 0x1f); // reg_splt_h_size in MFC_3D_2D_576_2D_576_RGB_BYPASS()
13 MDrv_WriteByteMask( REG_FSC_BK20_A6, 0xc0, 0xff); // reg_splt_h_size_l in MFC_3D_2D_576_2D_576_RGB_BYPASS()
14 MDrv_WriteByteMask( REG_FSC_BK20_A7, 0x03, 0x0f); // reg_splt_h_size_l in MFC_3D_2D_576_2D_576_RGB_BYPASS()
15 MDrv_WriteByteMask( REG_FSC_BK20_A8, 0x80, 0x80); // reg_mcm_lr_en in MFC_3D_2D_576_2D_576_RGB_BYPASS()
16 MDrv_WriteByteMask( REG_FSC_BK20_49, 0x04, 0x0f); // reg_vertical_limit_cnt in MFC_3D_2D_576_2D_576_RGB_BYPASS()
17 MDrv_WriteByteMask( REG_FSC_BK20_48, 0x38, 0xff); // reg_vertical_limit_cnt in MFC_3D_2D_576_2D_576_RGB_BYPASS()
18 MDrv_WriteByteMask( REG_FSC_BK20_1D, 0x00, 0x1f); // reg_hde_st in MFC_3D_2D_576_2D_576_RGB_BYPASS()
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| H A D | Maserati_2D_720.c | 9 MDrv_WriteByteMask( REG_FSC_BK20_A2, 0x80, 0xff); // reg_splt_gb_in_size_r in MFC_3D_2D_720_2D_720_RGB_BYPASS()
10 MDrv_WriteByteMask( REG_FSC_BK20_A3, 0x00, 0x01); // reg_splt_gb_in_size_r in MFC_3D_2D_720_2D_720_RGB_BYPASS()
11 MDrv_WriteByteMask( REG_FSC_BK20_A4, 0x80, 0xff); // reg_splt_h_size in MFC_3D_2D_720_2D_720_RGB_BYPASS()
12 MDrv_WriteByteMask( REG_FSC_BK20_A5, 0x07, 0x1f); // reg_splt_h_size in MFC_3D_2D_720_2D_720_RGB_BYPASS()
13 MDrv_WriteByteMask( REG_FSC_BK20_A6, 0xc0, 0xff); // reg_splt_h_size_l in MFC_3D_2D_720_2D_720_RGB_BYPASS()
14 MDrv_WriteByteMask( REG_FSC_BK20_A7, 0x03, 0x0f); // reg_splt_h_size_l in MFC_3D_2D_720_2D_720_RGB_BYPASS()
15 MDrv_WriteByteMask( REG_FSC_BK20_A8, 0x80, 0x80); // reg_mcm_lr_en in MFC_3D_2D_720_2D_720_RGB_BYPASS()
16 MDrv_WriteByteMask( REG_FSC_BK20_49, 0x04, 0x0f); // reg_vertical_limit_cnt in MFC_3D_2D_720_2D_720_RGB_BYPASS()
17 MDrv_WriteByteMask( REG_FSC_BK20_48, 0x38, 0xff); // reg_vertical_limit_cnt in MFC_3D_2D_720_2D_720_RGB_BYPASS()
18 MDrv_WriteByteMask( REG_FSC_BK20_1D, 0x00, 0x1f); // reg_hde_st in MFC_3D_2D_720_2D_720_RGB_BYPASS()
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| H A D | Maserati_2D_FHD.c | 9 MDrv_WriteByteMask( REG_FSC_BK20_A2, 0x80, 0xff); // reg_splt_gb_in_size_r in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
10 MDrv_WriteByteMask( REG_FSC_BK20_A3, 0x00, 0x01); // reg_splt_gb_in_size_r in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
11 MDrv_WriteByteMask( REG_FSC_BK20_A4, 0x80, 0xff); // reg_splt_h_size in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
12 MDrv_WriteByteMask( REG_FSC_BK20_A5, 0x07, 0x1f); // reg_splt_h_size in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
13 MDrv_WriteByteMask( REG_FSC_BK20_A6, 0xc0, 0xff); // reg_splt_h_size_l in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
14 MDrv_WriteByteMask( REG_FSC_BK20_A7, 0x03, 0x0f); // reg_splt_h_size_l in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
15 MDrv_WriteByteMask( REG_FSC_BK20_A8, 0x80, 0x80); // reg_mcm_lr_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
16 MDrv_WriteByteMask( REG_FSC_BK20_49, 0x04, 0x0f); // reg_vertical_limit_cnt in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
17 MDrv_WriteByteMask( REG_FSC_BK20_48, 0x38, 0xff); // reg_vertical_limit_cnt in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
18 MDrv_WriteByteMask( REG_FSC_BK20_1D, 0x00, 0x1f); // reg_hde_st in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
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| H A D | Maserati_ACT_4K0_5K.c | 9 MDrv_WriteByteMask( REG_FSC_BK20_A2, 0x80, 0xff); // reg_splt_gb_in_size_r in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
10 MDrv_WriteByteMask( REG_FSC_BK20_A3, 0x00, 0x01); // reg_splt_gb_in_size_r in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
11 MDrv_WriteByteMask( REG_FSC_BK20_A4, 0x00, 0xff); // reg_splt_h_size in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
12 MDrv_WriteByteMask( REG_FSC_BK20_A5, 0x0f, 0x1f); // reg_splt_h_size in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
13 MDrv_WriteByteMask( REG_FSC_BK20_A6, 0x80, 0xff); // reg_splt_h_size_l in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
14 MDrv_WriteByteMask( REG_FSC_BK20_A7, 0x07, 0x0f); // reg_splt_h_size_l in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
15 MDrv_WriteByteMask( REG_FSC_BK20_A8, 0x80, 0x80); // reg_mcm_lr_en in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
16 MDrv_WriteByteMask( REG_FSC_BK20_49, 0x08, 0x0f); // reg_vertical_limit_cnt in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
17 MDrv_WriteByteMask( REG_FSC_BK20_48, 0x70, 0xff); // reg_vertical_limit_cnt in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
18 MDrv_WriteByteMask( REG_FSC_BK20_1D, 0x00, 0x1f); // reg_hde_st in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
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| H A D | Maserati_FRC_ACT_4K1K_LLRR_240.c | 9 MDrv_WriteByteMask( REG_FSC_BK20_A2, 0x80, 0xff); // reg_splt_gb_in_size_r in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
10 MDrv_WriteByteMask( REG_FSC_BK20_A3, 0x00, 0x01); // reg_splt_gb_in_size_r in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
11 MDrv_WriteByteMask( REG_FSC_BK20_A4, 0x00, 0xff); // reg_splt_h_size in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
12 MDrv_WriteByteMask( REG_FSC_BK20_A5, 0x0f, 0x1f); // reg_splt_h_size in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
13 MDrv_WriteByteMask( REG_FSC_BK20_A6, 0x80, 0xff); // reg_splt_h_size_l in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
14 MDrv_WriteByteMask( REG_FSC_BK20_A7, 0x07, 0x0f); // reg_splt_h_size_l in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
15 MDrv_WriteByteMask( REG_FSC_BK20_A8, 0x80, 0x80); // reg_mcm_lr_en in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
16 MDrv_WriteByteMask( REG_FSC_BK20_49, 0x08, 0x0f); // reg_vertical_limit_cnt in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
17 MDrv_WriteByteMask( REG_FSC_BK20_48, 0x70, 0xff); // reg_vertical_limit_cnt in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
18 MDrv_WriteByteMask( REG_FSC_BK20_1D, 0x00, 0x1f); // reg_hde_st in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
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| H A D | Maserati_ACT_4K1K.c | 9 MDrv_WriteByteMask( REG_FSC_BK20_A2, 0x80, 0xff); // reg_splt_gb_in_size_r in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
10 MDrv_WriteByteMask( REG_FSC_BK20_A3, 0x00, 0x01); // reg_splt_gb_in_size_r in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
11 MDrv_WriteByteMask( REG_FSC_BK20_A4, 0x00, 0xff); // reg_splt_h_size in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
12 MDrv_WriteByteMask( REG_FSC_BK20_A5, 0x0f, 0x1f); // reg_splt_h_size in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
13 MDrv_WriteByteMask( REG_FSC_BK20_A6, 0x80, 0xff); // reg_splt_h_size_l in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
14 MDrv_WriteByteMask( REG_FSC_BK20_A7, 0x07, 0x0f); // reg_splt_h_size_l in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
15 MDrv_WriteByteMask( REG_FSC_BK20_A8, 0x80, 0x80); // reg_mcm_lr_en in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
16 MDrv_WriteByteMask( REG_FSC_BK20_49, 0x08, 0x0f); // reg_vertical_limit_cnt in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
17 MDrv_WriteByteMask( REG_FSC_BK20_48, 0x70, 0xff); // reg_vertical_limit_cnt in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
18 MDrv_WriteByteMask( REG_FSC_BK20_1D, 0x00, 0x1f); // reg_hde_st in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
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| H A D | Maserati_FRC_ACT_4K2K_120.c | 9 MDrv_WriteByteMask( REG_FSC_BK20_A2, 0x80, 0xff); // reg_splt_gb_in_size_r in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
10 MDrv_WriteByteMask( REG_FSC_BK20_A3, 0x00, 0x01); // reg_splt_gb_in_size_r in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
11 MDrv_WriteByteMask( REG_FSC_BK20_A4, 0x00, 0xff); // reg_splt_h_size in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
12 MDrv_WriteByteMask( REG_FSC_BK20_A5, 0x0f, 0x1f); // reg_splt_h_size in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
13 MDrv_WriteByteMask( REG_FSC_BK20_A6, 0x80, 0xff); // reg_splt_h_size_l in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
14 MDrv_WriteByteMask( REG_FSC_BK20_A7, 0x07, 0x0f); // reg_splt_h_size_l in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
15 MDrv_WriteByteMask( REG_FSC_BK20_A8, 0x80, 0x80); // reg_mcm_lr_en in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
16 MDrv_WriteByteMask( REG_FSC_BK20_49, 0x08, 0x0f); // reg_vertical_limit_cnt in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
17 MDrv_WriteByteMask( REG_FSC_BK20_48, 0x70, 0xff); // reg_vertical_limit_cnt in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
18 MDrv_WriteByteMask( REG_FSC_BK20_1D, 0x00, 0x1f); // reg_hde_st in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
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| H A D | Maserati_FRC_PAS_4K2K_120.c | 9 MDrv_WriteByteMask( REG_FSC_BK20_A2, 0x80, 0xff); // reg_splt_gb_in_size_r in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
10 MDrv_WriteByteMask( REG_FSC_BK20_A3, 0x00, 0x01); // reg_splt_gb_in_size_r in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
11 MDrv_WriteByteMask( REG_FSC_BK20_A4, 0x00, 0xff); // reg_splt_h_size in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
12 MDrv_WriteByteMask( REG_FSC_BK20_A5, 0x0f, 0x1f); // reg_splt_h_size in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
13 MDrv_WriteByteMask( REG_FSC_BK20_A6, 0x80, 0xff); // reg_splt_h_size_l in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
14 MDrv_WriteByteMask( REG_FSC_BK20_A7, 0x07, 0x0f); // reg_splt_h_size_l in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
15 MDrv_WriteByteMask( REG_FSC_BK20_A8, 0x80, 0x80); // reg_mcm_lr_en in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
16 MDrv_WriteByteMask( REG_FSC_BK20_49, 0x08, 0x0f); // reg_vertical_limit_cnt in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
17 MDrv_WriteByteMask( REG_FSC_BK20_48, 0x70, 0xff); // reg_vertical_limit_cnt in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
18 MDrv_WriteByteMask( REG_FSC_BK20_1D, 0x00, 0x1f); // reg_hde_st in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | Maserati_2D_4K2K.c | 9 MDrv_WriteByteMask( REG_FSC_BK20_A2, 0x80, 0xff); // reg_splt_gb_in_size_r in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
10 MDrv_WriteByteMask( REG_FSC_BK20_A3, 0x00, 0x01); // reg_splt_gb_in_size_r in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
11 MDrv_WriteByteMask( REG_FSC_BK20_A4, 0x80, 0xff); // reg_splt_h_size in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
12 MDrv_WriteByteMask( REG_FSC_BK20_A5, 0x07, 0x1f); // reg_splt_h_size in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
13 MDrv_WriteByteMask( REG_FSC_BK20_A6, 0xc0, 0xff); // reg_splt_h_size_l in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
14 MDrv_WriteByteMask( REG_FSC_BK20_A7, 0x03, 0x0f); // reg_splt_h_size_l in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
15 MDrv_WriteByteMask( REG_FSC_BK20_A8, 0x80, 0x80); // reg_mcm_lr_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
16 MDrv_WriteByteMask( REG_FSC_BK20_49, 0x04, 0x0f); // reg_vertical_limit_cnt in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
17 MDrv_WriteByteMask( REG_FSC_BK20_48, 0x38, 0xff); // reg_vertical_limit_cnt in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
18 MDrv_WriteByteMask( REG_FSC_BK20_1D, 0x00, 0x1f); // reg_hde_st in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
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| H A D | Maserati_2D_720.c | 9 MDrv_WriteByteMask( REG_FSC_BK20_A2, 0x80, 0xff); // reg_splt_gb_in_size_r in MFC_3D_2D_720_2D_720_RGB_BYPASS()
10 MDrv_WriteByteMask( REG_FSC_BK20_A3, 0x00, 0x01); // reg_splt_gb_in_size_r in MFC_3D_2D_720_2D_720_RGB_BYPASS()
11 MDrv_WriteByteMask( REG_FSC_BK20_A4, 0x80, 0xff); // reg_splt_h_size in MFC_3D_2D_720_2D_720_RGB_BYPASS()
12 MDrv_WriteByteMask( REG_FSC_BK20_A5, 0x07, 0x1f); // reg_splt_h_size in MFC_3D_2D_720_2D_720_RGB_BYPASS()
13 MDrv_WriteByteMask( REG_FSC_BK20_A6, 0xc0, 0xff); // reg_splt_h_size_l in MFC_3D_2D_720_2D_720_RGB_BYPASS()
14 MDrv_WriteByteMask( REG_FSC_BK20_A7, 0x03, 0x0f); // reg_splt_h_size_l in MFC_3D_2D_720_2D_720_RGB_BYPASS()
15 MDrv_WriteByteMask( REG_FSC_BK20_A8, 0x80, 0x80); // reg_mcm_lr_en in MFC_3D_2D_720_2D_720_RGB_BYPASS()
16 MDrv_WriteByteMask( REG_FSC_BK20_49, 0x04, 0x0f); // reg_vertical_limit_cnt in MFC_3D_2D_720_2D_720_RGB_BYPASS()
17 MDrv_WriteByteMask( REG_FSC_BK20_48, 0x38, 0xff); // reg_vertical_limit_cnt in MFC_3D_2D_720_2D_720_RGB_BYPASS()
18 MDrv_WriteByteMask( REG_FSC_BK20_1D, 0x00, 0x1f); // reg_hde_st in MFC_3D_2D_720_2D_720_RGB_BYPASS()
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| H A D | Maserati_2D_480.c | 9 MDrv_WriteByteMask( REG_FSC_BK20_A2, 0x80, 0xff); // reg_splt_gb_in_size_r in MFC_3D_2D_480_2D_480_RGB_BYPASS()
10 MDrv_WriteByteMask( REG_FSC_BK20_A3, 0x00, 0x01); // reg_splt_gb_in_size_r in MFC_3D_2D_480_2D_480_RGB_BYPASS()
11 MDrv_WriteByteMask( REG_FSC_BK20_A4, 0x80, 0xff); // reg_splt_h_size in MFC_3D_2D_480_2D_480_RGB_BYPASS()
12 MDrv_WriteByteMask( REG_FSC_BK20_A5, 0x07, 0x1f); // reg_splt_h_size in MFC_3D_2D_480_2D_480_RGB_BYPASS()
13 MDrv_WriteByteMask( REG_FSC_BK20_A6, 0xc0, 0xff); // reg_splt_h_size_l in MFC_3D_2D_480_2D_480_RGB_BYPASS()
14 MDrv_WriteByteMask( REG_FSC_BK20_A7, 0x03, 0x0f); // reg_splt_h_size_l in MFC_3D_2D_480_2D_480_RGB_BYPASS()
15 MDrv_WriteByteMask( REG_FSC_BK20_A8, 0x80, 0x80); // reg_mcm_lr_en in MFC_3D_2D_480_2D_480_RGB_BYPASS()
16 MDrv_WriteByteMask( REG_FSC_BK20_49, 0x04, 0x0f); // reg_vertical_limit_cnt in MFC_3D_2D_480_2D_480_RGB_BYPASS()
17 MDrv_WriteByteMask( REG_FSC_BK20_48, 0x38, 0xff); // reg_vertical_limit_cnt in MFC_3D_2D_480_2D_480_RGB_BYPASS()
18 MDrv_WriteByteMask( REG_FSC_BK20_1D, 0x00, 0x1f); // reg_hde_st in MFC_3D_2D_480_2D_480_RGB_BYPASS()
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| H A D | Maserati_2D_576.c | 9 MDrv_WriteByteMask( REG_FSC_BK20_A2, 0x80, 0xff); // reg_splt_gb_in_size_r in MFC_3D_2D_576_2D_576_RGB_BYPASS()
10 MDrv_WriteByteMask( REG_FSC_BK20_A3, 0x00, 0x01); // reg_splt_gb_in_size_r in MFC_3D_2D_576_2D_576_RGB_BYPASS()
11 MDrv_WriteByteMask( REG_FSC_BK20_A4, 0x80, 0xff); // reg_splt_h_size in MFC_3D_2D_576_2D_576_RGB_BYPASS()
12 MDrv_WriteByteMask( REG_FSC_BK20_A5, 0x07, 0x1f); // reg_splt_h_size in MFC_3D_2D_576_2D_576_RGB_BYPASS()
13 MDrv_WriteByteMask( REG_FSC_BK20_A6, 0xc0, 0xff); // reg_splt_h_size_l in MFC_3D_2D_576_2D_576_RGB_BYPASS()
14 MDrv_WriteByteMask( REG_FSC_BK20_A7, 0x03, 0x0f); // reg_splt_h_size_l in MFC_3D_2D_576_2D_576_RGB_BYPASS()
15 MDrv_WriteByteMask( REG_FSC_BK20_A8, 0x80, 0x80); // reg_mcm_lr_en in MFC_3D_2D_576_2D_576_RGB_BYPASS()
16 MDrv_WriteByteMask( REG_FSC_BK20_49, 0x04, 0x0f); // reg_vertical_limit_cnt in MFC_3D_2D_576_2D_576_RGB_BYPASS()
17 MDrv_WriteByteMask( REG_FSC_BK20_48, 0x38, 0xff); // reg_vertical_limit_cnt in MFC_3D_2D_576_2D_576_RGB_BYPASS()
18 MDrv_WriteByteMask( REG_FSC_BK20_1D, 0x00, 0x1f); // reg_hde_st in MFC_3D_2D_576_2D_576_RGB_BYPASS()
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| H A D | Maserati_2D_FHD.c | 9 MDrv_WriteByteMask( REG_FSC_BK20_A2, 0x80, 0xff); // reg_splt_gb_in_size_r in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
10 MDrv_WriteByteMask( REG_FSC_BK20_A3, 0x00, 0x01); // reg_splt_gb_in_size_r in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
11 MDrv_WriteByteMask( REG_FSC_BK20_A4, 0x80, 0xff); // reg_splt_h_size in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
12 MDrv_WriteByteMask( REG_FSC_BK20_A5, 0x07, 0x1f); // reg_splt_h_size in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
13 MDrv_WriteByteMask( REG_FSC_BK20_A6, 0xc0, 0xff); // reg_splt_h_size_l in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
14 MDrv_WriteByteMask( REG_FSC_BK20_A7, 0x03, 0x0f); // reg_splt_h_size_l in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
15 MDrv_WriteByteMask( REG_FSC_BK20_A8, 0x80, 0x80); // reg_mcm_lr_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
16 MDrv_WriteByteMask( REG_FSC_BK20_49, 0x04, 0x0f); // reg_vertical_limit_cnt in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
17 MDrv_WriteByteMask( REG_FSC_BK20_48, 0x38, 0xff); // reg_vertical_limit_cnt in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
18 MDrv_WriteByteMask( REG_FSC_BK20_1D, 0x00, 0x1f); // reg_hde_st in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
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| H A D | Maserati_ACT_4K1K.c | 9 MDrv_WriteByteMask( REG_FSC_BK20_A2, 0x80, 0xff); // reg_splt_gb_in_size_r in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
10 MDrv_WriteByteMask( REG_FSC_BK20_A3, 0x00, 0x01); // reg_splt_gb_in_size_r in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
11 MDrv_WriteByteMask( REG_FSC_BK20_A4, 0x00, 0xff); // reg_splt_h_size in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
12 MDrv_WriteByteMask( REG_FSC_BK20_A5, 0x0f, 0x1f); // reg_splt_h_size in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
13 MDrv_WriteByteMask( REG_FSC_BK20_A6, 0x80, 0xff); // reg_splt_h_size_l in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
14 MDrv_WriteByteMask( REG_FSC_BK20_A7, 0x07, 0x0f); // reg_splt_h_size_l in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
15 MDrv_WriteByteMask( REG_FSC_BK20_A8, 0x80, 0x80); // reg_mcm_lr_en in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
16 MDrv_WriteByteMask( REG_FSC_BK20_49, 0x08, 0x0f); // reg_vertical_limit_cnt in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
17 MDrv_WriteByteMask( REG_FSC_BK20_48, 0x70, 0xff); // reg_vertical_limit_cnt in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
18 MDrv_WriteByteMask( REG_FSC_BK20_1D, 0x00, 0x1f); // reg_hde_st in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
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| H A D | Maserati_FRC_ACT_4K2K_120.c | 9 MDrv_WriteByteMask( REG_FSC_BK20_A2, 0x80, 0xff); // reg_splt_gb_in_size_r in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
10 MDrv_WriteByteMask( REG_FSC_BK20_A3, 0x00, 0x01); // reg_splt_gb_in_size_r in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
11 MDrv_WriteByteMask( REG_FSC_BK20_A4, 0x00, 0xff); // reg_splt_h_size in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
12 MDrv_WriteByteMask( REG_FSC_BK20_A5, 0x0f, 0x1f); // reg_splt_h_size in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
13 MDrv_WriteByteMask( REG_FSC_BK20_A6, 0x80, 0xff); // reg_splt_h_size_l in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
14 MDrv_WriteByteMask( REG_FSC_BK20_A7, 0x07, 0x0f); // reg_splt_h_size_l in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
15 MDrv_WriteByteMask( REG_FSC_BK20_A8, 0x80, 0x80); // reg_mcm_lr_en in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
16 MDrv_WriteByteMask( REG_FSC_BK20_49, 0x08, 0x0f); // reg_vertical_limit_cnt in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
17 MDrv_WriteByteMask( REG_FSC_BK20_48, 0x70, 0xff); // reg_vertical_limit_cnt in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
18 MDrv_WriteByteMask( REG_FSC_BK20_1D, 0x00, 0x1f); // reg_hde_st in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
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| H A D | Maserati_FRC_ACT_4K0_5K_LLRR_240.c | 9 MDrv_WriteByteMask( REG_FSC_BK20_A2, 0x80, 0xff); // reg_splt_gb_in_size_r in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
10 MDrv_WriteByteMask( REG_FSC_BK20_A3, 0x00, 0x01); // reg_splt_gb_in_size_r in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
11 MDrv_WriteByteMask( REG_FSC_BK20_A4, 0x00, 0xff); // reg_splt_h_size in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
12 MDrv_WriteByteMask( REG_FSC_BK20_A5, 0x0f, 0x1f); // reg_splt_h_size in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
13 MDrv_WriteByteMask( REG_FSC_BK20_A6, 0x80, 0xff); // reg_splt_h_size_l in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
14 MDrv_WriteByteMask( REG_FSC_BK20_A7, 0x07, 0x0f); // reg_splt_h_size_l in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
15 MDrv_WriteByteMask( REG_FSC_BK20_A8, 0x80, 0x80); // reg_mcm_lr_en in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
16 MDrv_WriteByteMask( REG_FSC_BK20_49, 0x08, 0x0f); // reg_vertical_limit_cnt in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
17 MDrv_WriteByteMask( REG_FSC_BK20_48, 0x70, 0xff); // reg_vertical_limit_cnt in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
18 MDrv_WriteByteMask( REG_FSC_BK20_1D, 0x00, 0x1f); // reg_hde_st in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
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| H A D | Maserati_FRC_PAS_4K2K_60.c | 9 MDrv_WriteByteMask( REG_FSC_BK20_A2, 0x80, 0xff); // reg_splt_gb_in_size_r in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
10 MDrv_WriteByteMask( REG_FSC_BK20_A3, 0x00, 0x01); // reg_splt_gb_in_size_r in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
11 MDrv_WriteByteMask( REG_FSC_BK20_A4, 0x00, 0xff); // reg_splt_h_size in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
12 MDrv_WriteByteMask( REG_FSC_BK20_A5, 0x0f, 0x1f); // reg_splt_h_size in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
13 MDrv_WriteByteMask( REG_FSC_BK20_A6, 0x80, 0xff); // reg_splt_h_size_l in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
14 MDrv_WriteByteMask( REG_FSC_BK20_A7, 0x07, 0x0f); // reg_splt_h_size_l in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
15 MDrv_WriteByteMask( REG_FSC_BK20_A8, 0x80, 0x80); // reg_mcm_lr_en in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
16 MDrv_WriteByteMask( REG_FSC_BK20_49, 0x08, 0x0f); // reg_vertical_limit_cnt in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
17 MDrv_WriteByteMask( REG_FSC_BK20_48, 0x70, 0xff); // reg_vertical_limit_cnt in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
18 MDrv_WriteByteMask( REG_FSC_BK20_1D, 0x00, 0x1f); // reg_hde_st in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | Manhattan_2D_4K2K.c | 9 MDrv_WriteByteMask( REG_FSC_BK20_A2, 0x80, 0xff); // reg_splt_gb_in_size_r in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
10 MDrv_WriteByteMask( REG_FSC_BK20_A3, 0x00, 0x01); // reg_splt_gb_in_size_r in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
11 MDrv_WriteByteMask( REG_FSC_BK20_A4, 0x80, 0xff); // reg_splt_h_size in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
12 MDrv_WriteByteMask( REG_FSC_BK20_A5, 0x07, 0x1f); // reg_splt_h_size in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
13 MDrv_WriteByteMask( REG_FSC_BK20_A6, 0xc0, 0xff); // reg_splt_h_size_l in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
14 MDrv_WriteByteMask( REG_FSC_BK20_A7, 0x03, 0x0f); // reg_splt_h_size_l in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
15 MDrv_WriteByteMask( REG_FSC_BK20_A8, 0x80, 0x80); // reg_mcm_lr_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
16 MDrv_WriteByteMask( REG_FSC_BK20_49, 0x04, 0x0f); // reg_vertical_limit_cnt in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
17 MDrv_WriteByteMask( REG_FSC_BK20_48, 0x38, 0xff); // reg_vertical_limit_cnt in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
18 MDrv_WriteByteMask( REG_FSC_BK20_1D, 0x00, 0x1f); // reg_hde_st in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | Manhattan_2D_4K2K.c | 9 MDrv_WriteByteMask( REG_FSC_BK20_A2, 0x80, 0xff); // reg_splt_gb_in_size_r in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
10 MDrv_WriteByteMask( REG_FSC_BK20_A3, 0x00, 0x01); // reg_splt_gb_in_size_r in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
11 MDrv_WriteByteMask( REG_FSC_BK20_A4, 0x80, 0xff); // reg_splt_h_size in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
12 MDrv_WriteByteMask( REG_FSC_BK20_A5, 0x07, 0x1f); // reg_splt_h_size in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
13 MDrv_WriteByteMask( REG_FSC_BK20_A6, 0xc0, 0xff); // reg_splt_h_size_l in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
14 MDrv_WriteByteMask( REG_FSC_BK20_A7, 0x03, 0x0f); // reg_splt_h_size_l in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
15 MDrv_WriteByteMask( REG_FSC_BK20_A8, 0x80, 0x80); // reg_mcm_lr_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
16 MDrv_WriteByteMask( REG_FSC_BK20_49, 0x04, 0x0f); // reg_vertical_limit_cnt in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
17 MDrv_WriteByteMask( REG_FSC_BK20_48, 0x38, 0xff); // reg_vertical_limit_cnt in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
18 MDrv_WriteByteMask( REG_FSC_BK20_1D, 0x00, 0x1f); // reg_hde_st in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | Maxim_2D_4K2K.c | 9 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
10 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x02); // reg_hvsp_buffer_md in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
11 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
13 MDrv_WriteByteMask( REG_SC_BK4F_12, 0x00, 0xff); // vsp_scl_fac0 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
14 MDrv_WriteByteMask( REG_SC_BK4F_13, 0x00, 0xff); // vsp_scl_fac1 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
15 MDrv_WriteByteMask( REG_SC_BK4F_14, 0x08, 0xff); // vsp_scl_fac2 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
16 MDrv_WriteByteMask( REG_SC_BK4F_15, 0x01, 0x01); // vsp_scl_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
17 MDrv_WriteByteMask( REG_SC_BK4F_15, 0x02, 0x02); // vsp_shift_mode_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
18 MDrv_WriteByteMask( REG_SC_BK4F_06, 0x00, 0xff); // vsp_ini_scl_fac0 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
19 MDrv_WriteByteMask( REG_SC_BK4F_07, 0x00, 0xff); // vsp_ini_scl_fac1 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
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| H A D | Maxim_2D_FHD.c | 9 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
10 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x02, 0x02); // reg_hvsp_buffer_md in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
11 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
13 MDrv_WriteByteMask( REG_SC_BK4F_12, 0x00, 0xff); // vsp_scl_fac0 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
14 MDrv_WriteByteMask( REG_SC_BK4F_13, 0x00, 0xff); // vsp_scl_fac1 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
15 MDrv_WriteByteMask( REG_SC_BK4F_14, 0x10, 0xff); // vsp_scl_fac2 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
16 MDrv_WriteByteMask( REG_SC_BK4F_15, 0x01, 0x01); // vsp_scl_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
17 MDrv_WriteByteMask( REG_SC_BK4F_15, 0x00, 0x02); // vsp_shift_mode_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
18 MDrv_WriteByteMask( REG_SC_BK4F_06, 0x00, 0xff); // vsp_ini_scl_fac0 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
19 MDrv_WriteByteMask( REG_SC_BK4F_07, 0x00, 0xff); // vsp_ini_scl_fac1 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | Maxim_2D_4K2K.c | 9 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
10 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x02); // reg_hvsp_buffer_md in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
11 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
13 MDrv_WriteByteMask( REG_SC_BK4F_12, 0x00, 0xff); // vsp_scl_fac0 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
14 MDrv_WriteByteMask( REG_SC_BK4F_13, 0x00, 0xff); // vsp_scl_fac1 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
15 MDrv_WriteByteMask( REG_SC_BK4F_14, 0x08, 0xff); // vsp_scl_fac2 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
16 MDrv_WriteByteMask( REG_SC_BK4F_15, 0x01, 0x01); // vsp_scl_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
17 MDrv_WriteByteMask( REG_SC_BK4F_15, 0x02, 0x02); // vsp_shift_mode_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
18 MDrv_WriteByteMask( REG_SC_BK4F_06, 0x00, 0xff); // vsp_ini_scl_fac0 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
19 MDrv_WriteByteMask( REG_SC_BK4F_07, 0x00, 0xff); // vsp_ini_scl_fac1 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
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| H A D | Maxim_2D_FHD.c | 9 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
10 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x02); // reg_hvsp_buffer_md in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
11 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
13 MDrv_WriteByteMask( REG_SC_BK4F_12, 0x00, 0xff); // vsp_scl_fac0 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
14 MDrv_WriteByteMask( REG_SC_BK4F_13, 0x00, 0xff); // vsp_scl_fac1 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
15 MDrv_WriteByteMask( REG_SC_BK4F_14, 0x10, 0xff); // vsp_scl_fac2 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
16 MDrv_WriteByteMask( REG_SC_BK4F_15, 0x01, 0x01); // vsp_scl_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
17 MDrv_WriteByteMask( REG_SC_BK4F_15, 0x00, 0x02); // vsp_shift_mode_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
18 MDrv_WriteByteMask( REG_SC_BK4F_06, 0x00, 0xff); // vsp_ini_scl_fac0 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
19 MDrv_WriteByteMask( REG_SC_BK4F_07, 0x00, 0xff); // vsp_ini_scl_fac1 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
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