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Searched refs:L_BK_CHIPTOP_TOP (Results 1 – 8 of 8) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A DhalDAC.c1610 W1BYTE(L_BK_CHIPTOP_TOP(REG_HSYNC_VSYNC_EN), 0x03, 1:0); //Enable Hsync Vsync in Hal_DAC_SetVGAHsyncVsync()
1616 W1BYTE(L_BK_CHIPTOP_TOP(REG_HSYNC_VSYNC_EN), 0x00, 1:0); //Disable Hsync Vsync in Hal_DAC_SetVGAHsyncVsync()
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A DhalDAC.h167 #define L_BK_CHIPTOP_TOP(x) BK_REG_L(CHIPTOP_REG_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A DhalDAC.c2224 W1BYTE(L_BK_CHIPTOP_TOP(REG_HSYNC_VSYNC_EN), 0x03, 1:0); //Enable Hsync Vsync in Hal_DAC_SetVGAHsyncVsync()
2230 W1BYTE(L_BK_CHIPTOP_TOP(REG_HSYNC_VSYNC_EN), 0x00, 1:0); //Disable Hsync Vsync in Hal_DAC_SetVGAHsyncVsync()
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A DhalDAC.h171 #define L_BK_CHIPTOP_TOP(x) BK_REG_L(CHIPTOP_REG_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A DhalDAC.h171 #define L_BK_CHIPTOP_TOP(x) BK_REG_L(CHIPTOP_REG_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A DhalDAC.h171 #define L_BK_CHIPTOP_TOP(x) BK_REG_L(CHIPTOP_REG_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A DhalDAC.c2245 W1BYTE(L_BK_CHIPTOP_TOP(REG_HSYNC_VSYNC_EN), 0x03, 1:0); //Enable Hsync Vsync in Hal_DAC_SetVGAHsyncVsync()
2249 W1BYTE(L_BK_CHIPTOP_TOP(REG_HSYNC_VSYNC_EN), 0x00, 1:0); //Disable Hsync Vsync in Hal_DAC_SetVGAHsyncVsync()
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A DhalDAC.c2236 W1BYTE(L_BK_CHIPTOP_TOP(REG_HSYNC_VSYNC_EN), 0x03, 1:0); //Enable Hsync Vsync in Hal_DAC_SetVGAHsyncVsync()
2242 W1BYTE(L_BK_CHIPTOP_TOP(REG_HSYNC_VSYNC_EN), 0x00, 1:0); //Disable Hsync Vsync in Hal_DAC_SetVGAHsyncVsync()