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Searched refs:H_BK_ADC_ATOP (Results 1 – 25 of 57) sorted by relevance

123

/utopia/UTPA2-700.0.x/modules/vd/hal/mainz/avd/
H A DhalAVD.c3466 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0x00, (BIT(6)|BIT(4)|BIT(3))); in HAL_AVD_AFEC_SetClock()
3469 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0x00, (BIT(4))); in HAL_AVD_AFEC_SetClock()
3475 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0xFF, (BIT(6)|BIT(4)|BIT(3))); in HAL_AVD_AFEC_SetClock()
3478 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0xFF, (BIT(4))); in HAL_AVD_AFEC_SetClock()
3513 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0x00, (BIT(6)|BIT(3))); in HAL_AVD_AFEC_SetClockSource()
3516 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0x00, (BIT(4)|BIT(2))); in HAL_AVD_AFEC_SetClockSource()
3517 RIU_WriteByteMask(H_BK_ADC_ATOP(0x5E), 0x00, (BIT(5))); // new after T4 in HAL_AVD_AFEC_SetClockSource()
3519 RIU_WriteByte(H_BK_ADC_ATOP(0x04), 0xB7); in HAL_AVD_AFEC_SetClockSource()
3521 RIU_WriteByte(H_BK_ADC_ATOP(0x05), 0x07); in HAL_AVD_AFEC_SetClockSource()
3523 RIU_WriteByte(H_BK_ADC_ATOP(0x06), 0xEB); in HAL_AVD_AFEC_SetClockSource()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/mustang/avd/
H A DhalAVD.c6822 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0x00, (BIT(6)|BIT(4)|BIT(3))); in HAL_AVD_AFEC_SetClock()
6825 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0x00, (BIT(4))); in HAL_AVD_AFEC_SetClock()
6831 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0xFF, (BIT(6)|BIT(4)|BIT(3))); in HAL_AVD_AFEC_SetClock()
6834 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0xFF, (BIT(4))); in HAL_AVD_AFEC_SetClock()
6869 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0x00, (BIT(6)|BIT(3))); in HAL_AVD_AFEC_SetClockSource()
6872 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0x00, (BIT(4)|BIT(2))); in HAL_AVD_AFEC_SetClockSource()
6873 RIU_WriteByteMask(H_BK_ADC_ATOP(0x5E), 0x00, (BIT(5))); // new after T4 in HAL_AVD_AFEC_SetClockSource()
6875 RIU_WriteByte(H_BK_ADC_ATOP(0x04), 0xB7); in HAL_AVD_AFEC_SetClockSource()
6877 RIU_WriteByte(H_BK_ADC_ATOP(0x05), 0x07); in HAL_AVD_AFEC_SetClockSource()
6879 RIU_WriteByte(H_BK_ADC_ATOP(0x06), 0xEB); in HAL_AVD_AFEC_SetClockSource()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/M7821/avd/
H A DhalAVD.c6886 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0x00, (BIT(6)|BIT(4)|BIT(3))); in HAL_AVD_AFEC_SetClock()
6889 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0x00, (BIT(4))); in HAL_AVD_AFEC_SetClock()
6900 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0xFF, (BIT(6)|BIT(4)|BIT(3))); in HAL_AVD_AFEC_SetClock()
6903 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0xFF, (BIT(4))); in HAL_AVD_AFEC_SetClock()
6990 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0x00, (BIT(6)|BIT(3))); in HAL_AVD_AFEC_SetClockSource()
6993 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0x00, (BIT(4)|BIT(2))); in HAL_AVD_AFEC_SetClockSource()
6994 RIU_WriteByteMask(H_BK_ADC_ATOP(0x5E), 0x00, (BIT(5))); // new after T4 in HAL_AVD_AFEC_SetClockSource()
6996 RIU_WriteByte(H_BK_ADC_ATOP(0x04), 0xB7); in HAL_AVD_AFEC_SetClockSource()
6998 RIU_WriteByte(H_BK_ADC_ATOP(0x05), 0x07); in HAL_AVD_AFEC_SetClockSource()
7000 RIU_WriteByte(H_BK_ADC_ATOP(0x06), 0xEB); in HAL_AVD_AFEC_SetClockSource()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/kano/avd/
H A DhalAVD.c6886 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0x00, (BIT(6)|BIT(4)|BIT(3))); in HAL_AVD_AFEC_SetClock()
6889 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0x00, (BIT(4))); in HAL_AVD_AFEC_SetClock()
6900 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0xFF, (BIT(6)|BIT(4)|BIT(3))); in HAL_AVD_AFEC_SetClock()
6903 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0xFF, (BIT(4))); in HAL_AVD_AFEC_SetClock()
6990 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0x00, (BIT(6)|BIT(3))); in HAL_AVD_AFEC_SetClockSource()
6993 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0x00, (BIT(4)|BIT(2))); in HAL_AVD_AFEC_SetClockSource()
6994 RIU_WriteByteMask(H_BK_ADC_ATOP(0x5E), 0x00, (BIT(5))); // new after T4 in HAL_AVD_AFEC_SetClockSource()
6996 RIU_WriteByte(H_BK_ADC_ATOP(0x04), 0xB7); in HAL_AVD_AFEC_SetClockSource()
6998 RIU_WriteByte(H_BK_ADC_ATOP(0x05), 0x07); in HAL_AVD_AFEC_SetClockSource()
7000 RIU_WriteByte(H_BK_ADC_ATOP(0x06), 0xEB); in HAL_AVD_AFEC_SetClockSource()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/manhattan/avd/
H A DhalAVD.c6880 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0x00, (BIT(6)|BIT(4)|BIT(3))); in HAL_AVD_AFEC_SetClock()
6883 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0x00, (BIT(4))); in HAL_AVD_AFEC_SetClock()
6894 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0xFF, (BIT(6)|BIT(4)|BIT(3))); in HAL_AVD_AFEC_SetClock()
6897 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0xFF, (BIT(4))); in HAL_AVD_AFEC_SetClock()
6937 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0x00, (BIT(6)|BIT(3))); in HAL_AVD_AFEC_SetClockSource()
6940 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0x00, (BIT(4)|BIT(2))); in HAL_AVD_AFEC_SetClockSource()
6941 RIU_WriteByteMask(H_BK_ADC_ATOP(0x5E), 0x00, (BIT(5))); // new after T4 in HAL_AVD_AFEC_SetClockSource()
6943 RIU_WriteByte(H_BK_ADC_ATOP(0x04), 0xB7); in HAL_AVD_AFEC_SetClockSource()
6945 RIU_WriteByte(H_BK_ADC_ATOP(0x05), 0x07); in HAL_AVD_AFEC_SetClockSource()
6947 RIU_WriteByte(H_BK_ADC_ATOP(0x06), 0xEB); in HAL_AVD_AFEC_SetClockSource()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/M7621/avd/
H A DhalAVD.c6886 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0x00, (BIT(6)|BIT(4)|BIT(3))); in HAL_AVD_AFEC_SetClock()
6889 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0x00, (BIT(4))); in HAL_AVD_AFEC_SetClock()
6900 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0xFF, (BIT(6)|BIT(4)|BIT(3))); in HAL_AVD_AFEC_SetClock()
6903 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0xFF, (BIT(4))); in HAL_AVD_AFEC_SetClock()
6990 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0x00, (BIT(6)|BIT(3))); in HAL_AVD_AFEC_SetClockSource()
6993 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0x00, (BIT(4)|BIT(2))); in HAL_AVD_AFEC_SetClockSource()
6994 RIU_WriteByteMask(H_BK_ADC_ATOP(0x5E), 0x00, (BIT(5))); // new after T4 in HAL_AVD_AFEC_SetClockSource()
6996 RIU_WriteByte(H_BK_ADC_ATOP(0x04), 0xB7); in HAL_AVD_AFEC_SetClockSource()
6998 RIU_WriteByte(H_BK_ADC_ATOP(0x05), 0x07); in HAL_AVD_AFEC_SetClockSource()
7000 RIU_WriteByte(H_BK_ADC_ATOP(0x06), 0xEB); in HAL_AVD_AFEC_SetClockSource()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/maldives/avd/
H A DhalAVD.c6822 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0x00, (BIT(6)|BIT(4)|BIT(3))); in HAL_AVD_AFEC_SetClock()
6825 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0x00, (BIT(4))); in HAL_AVD_AFEC_SetClock()
6831 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0xFF, (BIT(6)|BIT(4)|BIT(3))); in HAL_AVD_AFEC_SetClock()
6834 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0xFF, (BIT(4))); in HAL_AVD_AFEC_SetClock()
6869 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0x00, (BIT(6)|BIT(3))); in HAL_AVD_AFEC_SetClockSource()
6872 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0x00, (BIT(4)|BIT(2))); in HAL_AVD_AFEC_SetClockSource()
6873 RIU_WriteByteMask(H_BK_ADC_ATOP(0x5E), 0x00, (BIT(5))); // new after T4 in HAL_AVD_AFEC_SetClockSource()
6875 RIU_WriteByte(H_BK_ADC_ATOP(0x04), 0xB7); in HAL_AVD_AFEC_SetClockSource()
6877 RIU_WriteByte(H_BK_ADC_ATOP(0x05), 0x07); in HAL_AVD_AFEC_SetClockSource()
6879 RIU_WriteByte(H_BK_ADC_ATOP(0x06), 0xEB); in HAL_AVD_AFEC_SetClockSource()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/messi/avd/
H A DhalAVD.c3466 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0x00, (BIT(6)|BIT(4)|BIT(3))); in HAL_AVD_AFEC_SetClock()
3469 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0x00, (BIT(4))); in HAL_AVD_AFEC_SetClock()
3475 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0xFF, (BIT(6)|BIT(4)|BIT(3))); in HAL_AVD_AFEC_SetClock()
3478 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0xFF, (BIT(4))); in HAL_AVD_AFEC_SetClock()
3513 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0x00, (BIT(6)|BIT(3))); in HAL_AVD_AFEC_SetClockSource()
3516 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0x00, (BIT(4)|BIT(2))); in HAL_AVD_AFEC_SetClockSource()
3517 RIU_WriteByteMask(H_BK_ADC_ATOP(0x5E), 0x00, (BIT(5))); // new after T4 in HAL_AVD_AFEC_SetClockSource()
3519 RIU_WriteByte(H_BK_ADC_ATOP(0x04), 0xB7); in HAL_AVD_AFEC_SetClockSource()
3521 RIU_WriteByte(H_BK_ADC_ATOP(0x05), 0x07); in HAL_AVD_AFEC_SetClockSource()
3523 RIU_WriteByte(H_BK_ADC_ATOP(0x06), 0xEB); in HAL_AVD_AFEC_SetClockSource()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/maserati/avd/
H A DhalAVD.c6886 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0x00, (BIT(6)|BIT(4)|BIT(3))); in HAL_AVD_AFEC_SetClock()
6889 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0x00, (BIT(4))); in HAL_AVD_AFEC_SetClock()
6900 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0xFF, (BIT(6)|BIT(4)|BIT(3))); in HAL_AVD_AFEC_SetClock()
6903 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0xFF, (BIT(4))); in HAL_AVD_AFEC_SetClock()
6990 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0x00, (BIT(6)|BIT(3))); in HAL_AVD_AFEC_SetClockSource()
6993 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0x00, (BIT(4)|BIT(2))); in HAL_AVD_AFEC_SetClockSource()
6994 RIU_WriteByteMask(H_BK_ADC_ATOP(0x5E), 0x00, (BIT(5))); // new after T4 in HAL_AVD_AFEC_SetClockSource()
6996 RIU_WriteByte(H_BK_ADC_ATOP(0x04), 0xB7); in HAL_AVD_AFEC_SetClockSource()
6998 RIU_WriteByte(H_BK_ADC_ATOP(0x05), 0x07); in HAL_AVD_AFEC_SetClockSource()
7000 RIU_WriteByte(H_BK_ADC_ATOP(0x06), 0xEB); in HAL_AVD_AFEC_SetClockSource()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/maxim/avd/
H A DhalAVD.c6886 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0x00, (BIT(6)|BIT(4)|BIT(3))); in HAL_AVD_AFEC_SetClock()
6889 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0x00, (BIT(4))); in HAL_AVD_AFEC_SetClock()
6900 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0xFF, (BIT(6)|BIT(4)|BIT(3))); in HAL_AVD_AFEC_SetClock()
6903 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0xFF, (BIT(4))); in HAL_AVD_AFEC_SetClock()
6990 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0x00, (BIT(6)|BIT(3))); in HAL_AVD_AFEC_SetClockSource()
6993 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0x00, (BIT(4)|BIT(2))); in HAL_AVD_AFEC_SetClockSource()
6994 RIU_WriteByteMask(H_BK_ADC_ATOP(0x5E), 0x00, (BIT(5))); // new after T4 in HAL_AVD_AFEC_SetClockSource()
6996 RIU_WriteByte(H_BK_ADC_ATOP(0x04), 0xB7); in HAL_AVD_AFEC_SetClockSource()
6998 RIU_WriteByte(H_BK_ADC_ATOP(0x05), 0x07); in HAL_AVD_AFEC_SetClockSource()
7000 RIU_WriteByte(H_BK_ADC_ATOP(0x06), 0xEB); in HAL_AVD_AFEC_SetClockSource()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/mooney/avd/
H A DhalAVD.c3465 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0x00, (BIT(6)|BIT(4)|BIT(3))); in HAL_AVD_AFEC_SetClock()
3468 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0x00, (BIT(4))); in HAL_AVD_AFEC_SetClock()
3474 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0xFF, (BIT(6)|BIT(4)|BIT(3))); in HAL_AVD_AFEC_SetClock()
3477 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0xFF, (BIT(4))); in HAL_AVD_AFEC_SetClock()
3512 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0x00, (BIT(6)|BIT(3))); in HAL_AVD_AFEC_SetClockSource()
3515 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0x00, (BIT(4)|BIT(2))); in HAL_AVD_AFEC_SetClockSource()
3516 RIU_WriteByteMask(H_BK_ADC_ATOP(0x5E), 0x00, (BIT(5))); // new after T4 in HAL_AVD_AFEC_SetClockSource()
3518 RIU_WriteByte(H_BK_ADC_ATOP(0x04), 0xB7); in HAL_AVD_AFEC_SetClockSource()
3520 RIU_WriteByte(H_BK_ADC_ATOP(0x05), 0x07); in HAL_AVD_AFEC_SetClockSource()
3522 RIU_WriteByte(H_BK_ADC_ATOP(0x06), 0xEB); in HAL_AVD_AFEC_SetClockSource()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/macan/avd/
H A DhalAVD.c6838 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0x00, (BIT(6)|BIT(4)|BIT(3))); in HAL_AVD_AFEC_SetClock()
6841 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0x00, (BIT(4))); in HAL_AVD_AFEC_SetClock()
6847 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0xFF, (BIT(6)|BIT(4)|BIT(3))); in HAL_AVD_AFEC_SetClock()
6850 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0xFF, (BIT(4))); in HAL_AVD_AFEC_SetClock()
6885 RIU_WriteByteMask(H_BK_ADC_ATOP(0x04), 0x00, (BIT(6)|BIT(3))); in HAL_AVD_AFEC_SetClockSource()
6888 RIU_WriteByteMask(H_BK_ADC_ATOP(0x06), 0x00, (BIT(4)|BIT(2))); in HAL_AVD_AFEC_SetClockSource()
6889 RIU_WriteByteMask(H_BK_ADC_ATOP(0x5E), 0x00, (BIT(5))); // new after T4 in HAL_AVD_AFEC_SetClockSource()
6891 RIU_WriteByte(H_BK_ADC_ATOP(0x04), 0xB7); in HAL_AVD_AFEC_SetClockSource()
6893 RIU_WriteByte(H_BK_ADC_ATOP(0x05), 0x07); in HAL_AVD_AFEC_SetClockSource()
6895 RIU_WriteByte(H_BK_ADC_ATOP(0x06), 0xEB); in HAL_AVD_AFEC_SetClockSource()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_adc.c1358 MDrv_WriteByteMask(H_BK_ADC_ATOP(0x09), 0x00 ,0x18 ); in Hal_ADC_InitInternalCalibration()
2359 _stAutoAdcSetting.u8H_BkAtop_2D = MDrv_ReadByte(H_BK_ADC_ATOP(0x2D) ); in Hal_ADC_auto_adc_backup()
2452 MDrv_WriteByte(H_BK_ADC_ATOP(0x2D), _stAutoAdcSetting.u8H_BkAtop_2D); in Hal_ADC_auto_adc_restore()
2561 u8Flag = MDrv_ReadByte(H_BK_ADC_ATOP(0x45)); in Hal_ADC_is_scart_rgb()
2568 MDrv_WriteByteMask(H_BK_ADC_ATOP(0x45), 0x20, 0x20); in Hal_ADC_is_scart_rgb()
H A Dmhal_ip.c721 … MDrv_WriteByte(H_BK_ADC_ATOP(0x1C), 0x38); // Turn on SOG input low bandwidth filter in Hal_SC_ip_sog_detect()
730 … MDrv_WriteByte(H_BK_ADC_ATOP(0x1C), 0x30); // Turn off SOG input low bandwidth filter in Hal_SC_ip_sog_detect()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_adc.c1358 MDrv_WriteByteMask(H_BK_ADC_ATOP(0x09), 0x00 ,0x18 ); in Hal_ADC_InitInternalCalibration()
2359 _stAutoAdcSetting.u8H_BkAtop_2D = MDrv_ReadByte(H_BK_ADC_ATOP(0x2D) ); in Hal_ADC_auto_adc_backup()
2452 MDrv_WriteByte(H_BK_ADC_ATOP(0x2D), _stAutoAdcSetting.u8H_BkAtop_2D); in Hal_ADC_auto_adc_restore()
2561 u8Flag = MDrv_ReadByte(H_BK_ADC_ATOP(0x45)); in Hal_ADC_is_scart_rgb()
2568 MDrv_WriteByteMask(H_BK_ADC_ATOP(0x45), 0x20, 0x20); in Hal_ADC_is_scart_rgb()
H A Dmhal_ip.c721 … MDrv_WriteByte(H_BK_ADC_ATOP(0x1C), 0x38); // Turn on SOG input low bandwidth filter in Hal_SC_ip_sog_detect()
730 … MDrv_WriteByte(H_BK_ADC_ATOP(0x1C), 0x30); // Turn off SOG input low bandwidth filter in Hal_SC_ip_sog_detect()
/utopia/UTPA2-700.0.x/modules/vd/hal/k6lite/vbi/
H A DregVBI.h183 #define H_BK_ADC_ATOP(x) BK_REG_H(ADC_ATOP_REG_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/curry/vbi/
H A DregVBI.h183 #define H_BK_ADC_ATOP(x) BK_REG_H(ADC_ATOP_REG_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/kano/vbi/
H A DregVBI.h183 #define H_BK_ADC_ATOP(x) BK_REG_H(ADC_ATOP_REG_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/k6/vbi/
H A DregVBI.h183 #define H_BK_ADC_ATOP(x) BK_REG_H(ADC_ATOP_REG_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/M7821/vbi/
H A DregVBI.h202 #define H_BK_ADC_ATOP(x) BK_REG_H(ADC_ATOP_REG_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/M7621/vbi/
H A DregVBI.h202 #define H_BK_ADC_ATOP(x) BK_REG_H(ADC_ATOP_REG_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/messi/vbi/
H A DregVBI.h199 #define H_BK_ADC_ATOP(x) BK_REG_H(ADC_ATOP_REG_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/mainz/vbi/
H A DregVBI.h199 #define H_BK_ADC_ATOP(x) BK_REG_H(ADC_ATOP_REG_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/macan/vbi/
H A DregVBI.h202 #define H_BK_ADC_ATOP(x) BK_REG_H(ADC_ATOP_REG_BASE, x) macro

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