Home
last modified time | relevance | path

Searched refs:HWI2C_REG_BASE (Results 1 – 25 of 30) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/hwi2c/hal/manhattan/hwi2c/
H A DregHWI2C.h164 #define HWI2C_REG_BASE (0x11800) //0x1(11800) + offset ==> default set to port 0 macro
165 #define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2)
174 #define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2)
176 #define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1)
178 #define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2)
179 #define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1)
181 #define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2)
182 #define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1)
185 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2)
187 #define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug
[all …]
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/M7821/hwi2c/
H A DregHWI2C.h164 #define HWI2C_REG_BASE (0x11800) //0x1(11800) + offset ==> default set to port 0 macro
165 #define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2)
174 #define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2)
176 #define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1)
178 #define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2)
179 #define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1)
181 #define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2)
182 #define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1)
185 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2)
187 #define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug
[all …]
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maserati/hwi2c/
H A DregHWI2C.h164 #define HWI2C_REG_BASE (0x11800) //0x1(11800) + offset ==> default set to port 0 macro
165 #define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2)
174 #define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2)
176 #define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1)
178 #define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2)
179 #define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1)
181 #define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2)
182 #define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1)
185 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2)
187 #define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug
[all …]
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/M7621/hwi2c/
H A DregHWI2C.h164 #define HWI2C_REG_BASE (0x11800) //0x1(11800) + offset ==> default set to port 0 macro
165 #define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2)
174 #define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2)
176 #define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1)
178 #define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2)
179 #define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1)
181 #define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2)
182 #define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1)
185 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2)
187 #define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug
[all …]
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maxim/hwi2c/
H A DregHWI2C.h164 #define HWI2C_REG_BASE (0x11800) //0x1(11800) + offset ==> default set to port 0 macro
165 #define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2)
174 #define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2)
176 #define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1)
178 #define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2)
179 #define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1)
181 #define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2)
182 #define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1)
185 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2)
187 #define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug
[all …]
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mainz/hwi2c/
H A DregHWI2C.h142 #define HWI2C_REG_BASE (0x11800) //0x1(11800) + offset ==> default set to port 0 macro
143 #define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2)
152 #define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2)
154 #define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1)
156 #define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2)
157 #define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1)
159 #define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2)
160 #define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1)
163 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2)
165 #define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug
[all …]
H A DhalHWI2C.c187 HWI2C_HAL_INFO("HWI2C IOMap base:%8lx Reg offset:%4x\n", u32Base, (MS_U16)HWI2C_REG_BASE); in HAL_HWI2C_SetIOMapBase()
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mooney/hwi2c/
H A DregHWI2C.h164 #define HWI2C_REG_BASE (0x11800) //0x1(11800) + offset ==> default set to port 0 macro
165 #define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2)
174 #define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2)
176 #define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1)
178 #define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2)
179 #define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1)
181 #define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2)
182 #define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1)
185 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2)
187 #define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug
[all …]
H A DhalHWI2C.c185 HWI2C_HAL_INFO("HWI2C IOMap base:%8lx Reg offset:%4x\n", u32Base, (MS_U16)HWI2C_REG_BASE); in HAL_HWI2C_SetIOMapBase()
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mustang/hwi2c/
H A DregHWI2C.h162 #define HWI2C_REG_BASE (0x02B00) //0x1(02B00) + offset ==> default set to port 0 macro
163 #define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2)
172 #define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2)
174 #define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1)
176 #define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2)
177 #define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1)
179 #define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2)
180 #define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1)
183 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2)
185 #define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug
[all …]
H A DhalHWI2C.c185 HWI2C_HAL_INFO("HWI2C IOMap base:%8lx Reg offset:%4x\n", u32Base, (MS_U16)HWI2C_REG_BASE); in HAL_HWI2C_SetIOMapBase()
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/messi/hwi2c/
H A DregHWI2C.h164 #define HWI2C_REG_BASE (0x11800) //0x1(11800) + offset ==> default set to port 0 macro
165 #define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2)
174 #define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2)
176 #define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1)
178 #define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2)
179 #define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1)
181 #define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2)
182 #define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1)
185 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2)
187 #define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug
[all …]
H A DhalHWI2C.c187 HWI2C_HAL_INFO("HWI2C IOMap base:%8lx Reg offset:%4x\n", u32Base, (MS_U16)HWI2C_REG_BASE); in HAL_HWI2C_SetIOMapBase()
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maldives/hwi2c/
H A DregHWI2C.h162 #define HWI2C_REG_BASE (0x02B00) //0x1(02B00) + offset ==> default set to port 0 macro
163 #define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2)
172 #define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2)
174 #define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1)
176 #define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2)
177 #define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1)
179 #define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2)
180 #define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1)
183 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2)
185 #define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug
[all …]
H A DhalHWI2C.c185 HWI2C_HAL_INFO("HWI2C IOMap base:%8lx Reg offset:%4x\n", u32Base, (MS_U16)HWI2C_REG_BASE); in HAL_HWI2C_SetIOMapBase()
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/macan/hwi2c/
H A DregHWI2C.h164 #define HWI2C_REG_BASE (0x11800) //0x1(11800) + offset ==> default set to port 0 macro
165 #define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2)
174 #define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2)
176 #define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1)
178 #define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2)
179 #define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1)
181 #define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2)
182 #define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1)
185 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2)
187 #define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug
[all …]
H A DhalHWI2C.c185 HWI2C_HAL_INFO("HWI2C IOMap base:%8lx Reg offset:%4x\n", u32Base, (MS_U16)HWI2C_REG_BASE); in HAL_HWI2C_SetIOMapBase()
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/k6lite/hwi2c/
H A DregHWI2C.h160 #define HWI2C_REG_BASE (0x13400) //0x1(13400) + offset ==> default set to port 0 macro
168 #define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2)
177 #define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2)
179 #define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1)
181 #define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2)
182 #define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1)
184 #define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2)
185 #define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1)
188 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2)
190 #define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug
[all …]
H A DhalHWI2C.c219 …_HAL_INFO("HWI2C IOMap base Non-PM:%8lx Reg offset:%8lx\n", _gMIO_MapBase, (MS_U32)HWI2C_REG_BASE); in HAL_HWI2C_SetIOMapBase()
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/kano/hwi2c/
H A DregHWI2C.h160 #define HWI2C_REG_BASE (0x13400) //0x1(13400) + offset ==> default set to port 0 macro
168 #define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2)
177 #define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2)
179 #define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1)
181 #define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2)
182 #define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1)
184 #define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2)
185 #define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1)
188 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2)
190 #define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug
[all …]
H A DhalHWI2C.c219 …_HAL_INFO("HWI2C IOMap base Non-PM:%8lx Reg offset:%8lx\n", _gMIO_MapBase, (MS_U32)HWI2C_REG_BASE); in HAL_HWI2C_SetIOMapBase()
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/k6/hwi2c/
H A DregHWI2C.h160 #define HWI2C_REG_BASE (0x13400) //0x1(13400) + offset ==> default set to port 0 macro
168 #define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2)
177 #define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2)
179 #define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1)
181 #define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2)
182 #define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1)
184 #define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2)
185 #define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1)
188 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2)
190 #define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug
[all …]
H A DhalHWI2C.c219 …_HAL_INFO("HWI2C IOMap base Non-PM:%8lx Reg offset:%8lx\n", _gMIO_MapBase, (MS_U32)HWI2C_REG_BASE); in HAL_HWI2C_SetIOMapBase()
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/curry/hwi2c/
H A DregHWI2C.h160 #define HWI2C_REG_BASE (0x13400) //0x1(13400) + offset ==> default set to port 0 macro
168 #define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2)
177 #define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2)
179 #define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1)
181 #define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2)
182 #define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1)
184 #define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2)
185 #define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1)
188 #define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2)
190 #define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug
[all …]
H A DhalHWI2C.c219 …_HAL_INFO("HWI2C IOMap base Non-PM:%8lx Reg offset:%8lx\n", _gMIO_MapBase, (MS_U32)HWI2C_REG_BASE); in HAL_HWI2C_SetIOMapBase()

12