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Searched refs:HDCP_W2BYTEMSK (Results 1 – 16 of 16) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_hdmi.c2001 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for … in _Hal_tmds_HDCPWriteX74()
2002 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU writ… in _Hal_tmds_HDCPWriteX74()
2004 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, ucAddress, BMASK(9:0)); // address in _Hal_tmds_HDCPWriteX74()
2005 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(5), BIT(5)); // trigger latch address in _Hal_tmds_HDCPWriteX74()
2009 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_18_L +u16bank_offset, ucData[uctemp], BMASK(7:0)); // data in _Hal_tmds_HDCPWriteX74()
2010 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(4), BIT(4)); // trigger latch data in _Hal_tmds_HDCPWriteX74()
2016 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, 0, BIT(15)|BIT(14)); // [15]: CPU write disa… in _Hal_tmds_HDCPWriteX74()
2489 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, BIT(10), BIT(10)); // [10]: HDCP enable for DDC in Hal_HDCP_initproductionkey()
2490 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write enable, [14]: … in Hal_HDCP_initproductionkey()
2492 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c3331 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for … in _Hal_tmds_HDCPWriteX74()
3332 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU writ… in _Hal_tmds_HDCPWriteX74()
3334 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, ucAddress, BMASK(9:0)); // address in _Hal_tmds_HDCPWriteX74()
3335 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(5), BIT(5)); // trigger latch address in _Hal_tmds_HDCPWriteX74()
3339 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_18_L +u16bank_offset, ucData[uctemp], BMASK(7:0)); // data in _Hal_tmds_HDCPWriteX74()
3340 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(4), BIT(4)); // trigger latch data in _Hal_tmds_HDCPWriteX74()
3346 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, 0, BIT(15)|BIT(14)); // [15]: CPU write disa… in _Hal_tmds_HDCPWriteX74()
3892 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_initproductionkey()
3893 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write… in Hal_HDCP_initproductionkey()
3895 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c3331 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for … in _Hal_tmds_HDCPWriteX74()
3332 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU writ… in _Hal_tmds_HDCPWriteX74()
3334 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, ucAddress, BMASK(9:0)); // address in _Hal_tmds_HDCPWriteX74()
3335 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(5), BIT(5)); // trigger latch address in _Hal_tmds_HDCPWriteX74()
3339 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_18_L +u16bank_offset, ucData[uctemp], BMASK(7:0)); // data in _Hal_tmds_HDCPWriteX74()
3340 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(4), BIT(4)); // trigger latch data in _Hal_tmds_HDCPWriteX74()
3346 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, 0, BIT(15)|BIT(14)); // [15]: CPU write disa… in _Hal_tmds_HDCPWriteX74()
3892 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_initproductionkey()
3893 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write… in Hal_HDCP_initproductionkey()
3895 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c3872 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for … in _Hal_tmds_HDCPWriteX74()
3873 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU writ… in _Hal_tmds_HDCPWriteX74()
3875 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, ucAddress, BMASK(9:0)); // address in _Hal_tmds_HDCPWriteX74()
3876 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(5), BIT(5)); // trigger latch address in _Hal_tmds_HDCPWriteX74()
3880 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_18_L +u16bank_offset, ucData[uctemp], BMASK(7:0)); // data in _Hal_tmds_HDCPWriteX74()
3881 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(4), BIT(4)); // trigger latch data in _Hal_tmds_HDCPWriteX74()
3887 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, 0, BIT(15)|BIT(14)); // [15]: CPU write disa… in _Hal_tmds_HDCPWriteX74()
4454 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_initproductionkey()
4455 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write… in Hal_HDCP_initproductionkey()
4457 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c3875 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for … in _Hal_tmds_HDCPWriteX74()
3876 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU writ… in _Hal_tmds_HDCPWriteX74()
3878 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, ucAddress, BMASK(9:0)); // address in _Hal_tmds_HDCPWriteX74()
3879 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(5), BIT(5)); // trigger latch address in _Hal_tmds_HDCPWriteX74()
3883 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_18_L +u16bank_offset, ucData[uctemp], BMASK(7:0)); // data in _Hal_tmds_HDCPWriteX74()
3884 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(4), BIT(4)); // trigger latch data in _Hal_tmds_HDCPWriteX74()
3890 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, 0, BIT(15)|BIT(14)); // [15]: CPU write disa… in _Hal_tmds_HDCPWriteX74()
4457 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_initproductionkey()
4458 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write… in Hal_HDCP_initproductionkey()
4460 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c3875 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for … in _Hal_tmds_HDCPWriteX74()
3876 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU writ… in _Hal_tmds_HDCPWriteX74()
3878 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L +u16bank_offset, ucAddress, BMASK(9:0)); // address in _Hal_tmds_HDCPWriteX74()
3879 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(5), BIT(5)); // trigger latch address in _Hal_tmds_HDCPWriteX74()
3883 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_18_L +u16bank_offset, ucData[uctemp], BMASK(7:0)); // data in _Hal_tmds_HDCPWriteX74()
3884 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, BIT(4), BIT(4)); // trigger latch data in _Hal_tmds_HDCPWriteX74()
3890 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L +u16bank_offset, 0, BIT(15)|BIT(14)); // [15]: CPU write disa… in _Hal_tmds_HDCPWriteX74()
4460 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_initproductionkey()
4461 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write… in Hal_HDCP_initproductionkey()
4463 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c3782 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_initproductionkey()
3783 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write… in Hal_HDCP_initproductionkey()
3785 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
3786 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
3789 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_18_L+u16bank_offset, *pu8HdcpKeyData, BMASK(7:0)); // data in Hal_HDCP_initproductionkey()
3790 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
3798 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x40, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
3799 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
3801 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_18_L+u16bank_offset, 0x80, BMASK(7:0)); // data in Hal_HDCP_initproductionkey()
3802 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c3882 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_initproductionkey()
3883 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write… in Hal_HDCP_initproductionkey()
3885 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
3886 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
3889 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_18_L+u16bank_offset, *pu8HdcpKeyData, BMASK(7:0)); // data in Hal_HDCP_initproductionkey()
3890 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
3898 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x40, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
3899 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
3901 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_18_L+u16bank_offset, 0x80, BMASK(7:0)); // data in Hal_HDCP_initproductionkey()
3902 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c3827 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_initproductionkey()
3828 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write… in Hal_HDCP_initproductionkey()
3830 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
3831 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
3834 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_18_L+u16bank_offset, *pu8HdcpKeyData, BMASK(7:0)); // data in Hal_HDCP_initproductionkey()
3835 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
3843 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x40, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
3844 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
3846 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_18_L+u16bank_offset, 0x80, BMASK(7:0)); // data in Hal_HDCP_initproductionkey()
3847 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c3882 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_initproductionkey()
3883 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write… in Hal_HDCP_initproductionkey()
3885 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
3886 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
3889 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_18_L+u16bank_offset, *pu8HdcpKeyData, BMASK(7:0)); // data in Hal_HDCP_initproductionkey()
3890 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
3898 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x40, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
3899 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
3901 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_18_L+u16bank_offset, 0x80, BMASK(7:0)); // data in Hal_HDCP_initproductionkey()
3902 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c4016 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_initproductionkey()
4017 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write… in Hal_HDCP_initproductionkey()
4019 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
4020 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
4023 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_18_L+u16bank_offset, *pu8HdcpKeyData, BMASK(7:0)); // data in Hal_HDCP_initproductionkey()
4024 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
4032 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x40, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
4033 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
4035 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_18_L+u16bank_offset, 0x80, BMASK(7:0)); // data in Hal_HDCP_initproductionkey()
4036 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c4016 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for D… in Hal_HDCP_initproductionkey()
4017 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write… in Hal_HDCP_initproductionkey()
4019 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
4020 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
4023 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_18_L+u16bank_offset, *pu8HdcpKeyData, BMASK(7:0)); // data in Hal_HDCP_initproductionkey()
4024 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
4032 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L+u16bank_offset, 0x40, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
4033 … HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
4035 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_18_L+u16bank_offset, 0x80, BMASK(7:0)); // data in Hal_HDCP_initproductionkey()
4036 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_hdmi.c1758 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, BIT(10), BIT(10)); // [10]: HDCP enable for DDC in Hal_HDCP_initproductionkey()
1759 …HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write enable, [14]: … in Hal_HDCP_initproductionkey()
1761 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
1762 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
1765 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_18_L, *pu8HdcpKeyData, BMASK(7:0)); // data in Hal_HDCP_initproductionkey()
1766 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
1776 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_17_L, 0x40, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
1777 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
1779 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_18_L, 0x80, BMASK(7:0)); // data in Hal_HDCP_initproductionkey()
1780 HDCP_W2BYTEMSK(REG_HDCP_DUAL_P0_19_L, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_hdmi.c895 HDCP_W2BYTEMSK(REG_HDCP_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for DDC in Hal_HDCP_initproductionkey()
896 …HDCP_W2BYTEMSK(REG_HDCP_19_L+u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write enable,… in Hal_HDCP_initproductionkey()
898 HDCP_W2BYTEMSK(REG_HDCP_17_L+u16bank_offset, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
899 HDCP_W2BYTEMSK(REG_HDCP_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
903 HDCP_W2BYTEMSK(REG_HDCP_18_L+u16bank_offset, *pu8HdcpKeyData, BMASK(7:0)); // data in Hal_HDCP_initproductionkey()
904 HDCP_W2BYTEMSK(REG_HDCP_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
911 HDCP_W2BYTEMSK(REG_HDCP_17_L+u16bank_offset, 0x40, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
912 HDCP_W2BYTEMSK(REG_HDCP_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
914 HDCP_W2BYTEMSK(REG_HDCP_18_L+u16bank_offset, 0x80, BMASK(7:0)); // data in Hal_HDCP_initproductionkey()
915 HDCP_W2BYTEMSK(REG_HDCP_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_hdmi.c895 HDCP_W2BYTEMSK(REG_HDCP_17_L+u16bank_offset, BIT(10), BIT(10)); // [10]: HDCP enable for DDC in Hal_HDCP_initproductionkey()
896 …HDCP_W2BYTEMSK(REG_HDCP_19_L+u16bank_offset, BIT(15), BIT(15)|BIT(14)); // [15]: CPU write enable,… in Hal_HDCP_initproductionkey()
898 HDCP_W2BYTEMSK(REG_HDCP_17_L+u16bank_offset, 0x00, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
899 HDCP_W2BYTEMSK(REG_HDCP_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
903 HDCP_W2BYTEMSK(REG_HDCP_18_L+u16bank_offset, *pu8HdcpKeyData, BMASK(7:0)); // data in Hal_HDCP_initproductionkey()
904 HDCP_W2BYTEMSK(REG_HDCP_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
911 HDCP_W2BYTEMSK(REG_HDCP_17_L+u16bank_offset, 0x40, BMASK(9:0)); // address in Hal_HDCP_initproductionkey()
912 HDCP_W2BYTEMSK(REG_HDCP_19_L+u16bank_offset, BIT(5), BIT(5)); // trigger latch address in Hal_HDCP_initproductionkey()
914 HDCP_W2BYTEMSK(REG_HDCP_18_L+u16bank_offset, 0x80, BMASK(7:0)); // data in Hal_HDCP_initproductionkey()
915 HDCP_W2BYTEMSK(REG_HDCP_19_L+u16bank_offset, BIT(4), BIT(4)); // trigger latch data in Hal_HDCP_initproductionkey()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/include/
H A Dxc_hwreg_utility2.h702 #define HDCP_W2BYTEMSK( u32Reg, u16Val, u16Mask)\ macro