| /utopia/UTPA2-700.0.x/modules/pm/hal/macan/pm/ |
| H A D | halPM.c | 283 MS_BOOL HAL_PM_WriteRegBit(MS_U32 u32RegAddr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_PM_WriteRegBit() function
364 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_CNT_EN); // Disable init in HAL_PM_RtcInit()
365 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RtcInit()
379 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_CNT_EN); // Disable init in HAL_PM_RtcInit()
380 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RtcInit()
401 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
402 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
405 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
406 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
535 HAL_PM_WriteRegBit(0x000e41UL, DISABLE, __BIT6); //spi_clk=xtal in HAL_PM_SetSPIOffsetForMCU()
[all …]
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| /utopia/UTPA2-700.0.x/modules/pm/hal/mainz/pm/ |
| H A D | halPM.c | 285 MS_BOOL HAL_PM_WriteRegBit(MS_U32 u32RegAddr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_PM_WriteRegBit() function
401 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
402 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
405 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
406 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
535 HAL_PM_WriteRegBit(0x000e41UL, DISABLE, __BIT6); //spi_clk=xtal in HAL_PM_SetSPIOffsetForMCU()
537 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSPIOffsetForMCU()
539 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSPIOffsetForMCU()
541 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE, __BIT0); //disable i cache in HAL_PM_SetSPIOffsetForMCU()
599 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSRAMOffsetForMCU()
[all …]
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| /utopia/UTPA2-700.0.x/modules/pm/hal/maserati/pm/ |
| H A D | halPM.c | 283 MS_BOOL HAL_PM_WriteRegBit(MS_U32 u32RegAddr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_PM_WriteRegBit() function
399 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
400 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
403 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
404 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
533 HAL_PM_WriteRegBit(0x000e41UL, DISABLE, __BIT6); //spi_clk=xtal in HAL_PM_SetSPIOffsetForMCU()
535 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSPIOffsetForMCU()
537 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSPIOffsetForMCU()
539 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE, __BIT0); //disable i cache in HAL_PM_SetSPIOffsetForMCU()
597 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSRAMOffsetForMCU()
[all …]
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| /utopia/UTPA2-700.0.x/modules/pm/hal/manhattan/pm/ |
| H A D | halPM.c | 283 MS_BOOL HAL_PM_WriteRegBit(MS_U32 u32RegAddr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_PM_WriteRegBit() function
399 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
400 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
403 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
404 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
533 HAL_PM_WriteRegBit(0x000e41UL, DISABLE, __BIT6); //spi_clk=xtal in HAL_PM_SetSPIOffsetForMCU()
535 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSPIOffsetForMCU()
537 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSPIOffsetForMCU()
539 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE, __BIT0); //disable i cache in HAL_PM_SetSPIOffsetForMCU()
597 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSRAMOffsetForMCU()
[all …]
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| /utopia/UTPA2-700.0.x/modules/pm/hal/M7621/pm/ |
| H A D | halPM.c | 283 MS_BOOL HAL_PM_WriteRegBit(MS_U32 u32RegAddr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_PM_WriteRegBit() function
399 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
400 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
403 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
404 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
533 HAL_PM_WriteRegBit(0x000e41UL, DISABLE, __BIT6); //spi_clk=xtal in HAL_PM_SetSPIOffsetForMCU()
535 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSPIOffsetForMCU()
537 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSPIOffsetForMCU()
539 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE, __BIT0); //disable i cache in HAL_PM_SetSPIOffsetForMCU()
597 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSRAMOffsetForMCU()
[all …]
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| /utopia/UTPA2-700.0.x/modules/pm/hal/maxim/pm/ |
| H A D | halPM.c | 283 MS_BOOL HAL_PM_WriteRegBit(MS_U32 u32RegAddr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_PM_WriteRegBit() function
399 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
400 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
403 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
404 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
533 HAL_PM_WriteRegBit(0x000e41UL, DISABLE, __BIT6); //spi_clk=xtal in HAL_PM_SetSPIOffsetForMCU()
535 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSPIOffsetForMCU()
537 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSPIOffsetForMCU()
539 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE, __BIT0); //disable i cache in HAL_PM_SetSPIOffsetForMCU()
597 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSRAMOffsetForMCU()
[all …]
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| /utopia/UTPA2-700.0.x/modules/pm/hal/mooney/pm/ |
| H A D | halPM.c | 283 MS_BOOL HAL_PM_WriteRegBit(MS_U32 u32RegAddr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_PM_WriteRegBit() function
399 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
400 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
403 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
404 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
533 HAL_PM_WriteRegBit(0x000e41UL, DISABLE, __BIT6); //spi_clk=xtal in HAL_PM_SetSPIOffsetForMCU()
535 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSPIOffsetForMCU()
537 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSPIOffsetForMCU()
539 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE, __BIT0); //disable i cache in HAL_PM_SetSPIOffsetForMCU()
597 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSRAMOffsetForMCU()
[all …]
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| /utopia/UTPA2-700.0.x/modules/pm/hal/M7821/pm/ |
| H A D | halPM.c | 283 MS_BOOL HAL_PM_WriteRegBit(MS_U32 u32RegAddr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_PM_WriteRegBit() function
399 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
400 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
403 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
404 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
533 HAL_PM_WriteRegBit(0x000e41UL, DISABLE, __BIT6); //spi_clk=xtal in HAL_PM_SetSPIOffsetForMCU()
535 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSPIOffsetForMCU()
537 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSPIOffsetForMCU()
539 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE, __BIT0); //disable i cache in HAL_PM_SetSPIOffsetForMCU()
597 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSRAMOffsetForMCU()
[all …]
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| /utopia/UTPA2-700.0.x/modules/pm/hal/messi/pm/ |
| H A D | halPM.c | 285 MS_BOOL HAL_PM_WriteRegBit(MS_U32 u32RegAddr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_PM_WriteRegBit() function
401 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
402 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
405 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
406 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
535 HAL_PM_WriteRegBit(0x000e41UL, DISABLE, __BIT6); //spi_clk=xtal in HAL_PM_SetSPIOffsetForMCU()
537 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSPIOffsetForMCU()
539 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSPIOffsetForMCU()
541 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE, __BIT0); //disable i cache in HAL_PM_SetSPIOffsetForMCU()
599 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSRAMOffsetForMCU()
[all …]
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| /utopia/UTPA2-700.0.x/modules/pm/hal/maldives/pm/ |
| H A D | halPM.c | 283 MS_BOOL HAL_PM_WriteRegBit(MS_U32 u32RegAddr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_PM_WriteRegBit() function
400 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
401 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
404 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
405 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
534 HAL_PM_WriteRegBit(0x000e41, DISABLE, __BIT6); //spi_clk=xtal in HAL_PM_SetSPIOffsetForMCU()
536 HAL_PM_WriteRegBit(0x000e40, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSPIOffsetForMCU()
538 HAL_PM_WriteRegBit(0x001018, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSPIOffsetForMCU()
540 HAL_PM_WriteRegBit(0x002ba0, ENABLE, __BIT0); //disable i cache in HAL_PM_SetSPIOffsetForMCU()
598 HAL_PM_WriteRegBit(0x000e40, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSRAMOffsetForMCU()
[all …]
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| /utopia/UTPA2-700.0.x/modules/pm/hal/mustang/pm/ |
| H A D | halPM.c | 283 MS_BOOL HAL_PM_WriteRegBit(MS_U32 u32RegAddr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_PM_WriteRegBit() function
400 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
401 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
404 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
405 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
534 HAL_PM_WriteRegBit(0x000e41, DISABLE, __BIT6); //spi_clk=xtal in HAL_PM_SetSPIOffsetForMCU()
536 HAL_PM_WriteRegBit(0x000e40, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSPIOffsetForMCU()
538 HAL_PM_WriteRegBit(0x001018, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSPIOffsetForMCU()
540 HAL_PM_WriteRegBit(0x002ba0, ENABLE, __BIT0); //disable i cache in HAL_PM_SetSPIOffsetForMCU()
598 HAL_PM_WriteRegBit(0x000e40, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSRAMOffsetForMCU()
[all …]
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| /utopia/UTPA2-700.0.x/modules/pm/hal/k6lite/pm/ |
| H A D | halPM.c | 304 MS_BOOL HAL_PM_WriteRegBit(MS_U32 u32RegAddr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_PM_WriteRegBit() function
532 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
533 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
536 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
537 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
669 HAL_PM_WriteRegBit(0x000e41UL, DISABLE, __BIT6); //spi_clk=xtal in HAL_PM_SetSPIOffsetForMCU()
671 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSPIOffsetForMCU()
673 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSPIOffsetForMCU()
675 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE, __BIT0); //disable i cache in HAL_PM_SetSPIOffsetForMCU()
719 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSRAMOffsetForMCU()
[all …]
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| /utopia/UTPA2-700.0.x/modules/pm/hal/k6/pm/ |
| H A D | halPM.c | 303 MS_BOOL HAL_PM_WriteRegBit(MS_U32 u32RegAddr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_PM_WriteRegBit() function
531 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
532 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
535 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
536 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
668 HAL_PM_WriteRegBit(0x000e41UL, DISABLE, __BIT6); //spi_clk=xtal in HAL_PM_SetSPIOffsetForMCU()
670 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSPIOffsetForMCU()
672 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSPIOffsetForMCU()
674 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE, __BIT0); //disable i cache in HAL_PM_SetSPIOffsetForMCU()
718 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSRAMOffsetForMCU()
[all …]
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| /utopia/UTPA2-700.0.x/modules/pm/hal/curry/pm/ |
| H A D | halPM.c | 304 MS_BOOL HAL_PM_WriteRegBit(MS_U32 u32RegAddr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_PM_WriteRegBit() function
532 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
533 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
536 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
537 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
669 HAL_PM_WriteRegBit(0x000e41UL, DISABLE, __BIT6); //spi_clk=xtal in HAL_PM_SetSPIOffsetForMCU()
671 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSPIOffsetForMCU()
673 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSPIOffsetForMCU()
675 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE, __BIT0); //disable i cache in HAL_PM_SetSPIOffsetForMCU()
719 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSRAMOffsetForMCU()
[all …]
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| /utopia/UTPA2-700.0.x/modules/pm/hal/kano/pm/ |
| H A D | halPM.c | 304 MS_BOOL HAL_PM_WriteRegBit(MS_U32 u32RegAddr, MS_BOOL bEnable, MS_U8 u8Mask) in HAL_PM_WriteRegBit() function
532 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
533 HAL_PM_WriteRegBit(REG_PMRTC_CTRL, DISABLE, PMRTC_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
536 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_CNT_EN); // Disable init in HAL_PM_RTC_DisableInit()
537 HAL_PM_WriteRegBit(REG_PMRTC1_CTRL, DISABLE, PMRTC1_CTRL_NOT_RSTZ); // Disable RSTZ in HAL_PM_RTC_DisableInit()
669 HAL_PM_WriteRegBit(0x000e41UL, DISABLE, __BIT6); //spi_clk=xtal in HAL_PM_SetSPIOffsetForMCU()
671 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSPIOffsetForMCU()
673 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSPIOffsetForMCU()
675 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE, __BIT0); //disable i cache in HAL_PM_SetSPIOffsetForMCU()
719 HAL_PM_WriteRegBit(0x000e40UL, DISABLE, __BIT7); //mcu51 clk=xtal in HAL_PM_SetSRAMOffsetForMCU()
[all …]
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| /utopia/UTPA2-700.0.x/modules/pwm/hal/mustang/pwm/ |
| H A D | halPWM.c | 126 #define HAL_PM_WriteRegBit(addr, val, mask) WRITE_WORD_MASK((_gMIO_PM_MapBase + REG_PM_BASE) + … macro
1332 HAL_PM_WriteRegBit(REG_PM_PWM0_IS_GPIO, BITS(5:5, 0), BMASK(5:5)); in HAL_PM_PWM_Enable()
1333 HAL_PM_WriteRegBit(reg_pwm_as_chip_config, BITS(0:0, 0), BMASK(0:0));//reg_pwm_pm_is_PWM in HAL_PM_PWM_Enable()
1359 HAL_PM_WriteRegBit(REG_PM_PWM0_PORARITY, BITS(0:0, bPolPWM), BMASK(0:0)); in HAL_PM_PWM_Polarity()
1364 HAL_PM_WriteRegBit(REG_PM_PWM0_DBEN, BITS(1:1, bdbenPWM), BMASK(1:1)); in HAL_PM_PWM_DBen()
1376 HAL_PM_WriteRegBit(REG_INV_3D_FLAG,BITS(15:15,bInvPWM),BMASK(15:15)); in HAL_PWM_INV_3D_Flag()
|
| /utopia/UTPA2-700.0.x/modules/pwm/hal/maldives/pwm/ |
| H A D | halPWM.c | 126 #define HAL_PM_WriteRegBit(addr, val, mask) WRITE_WORD_MASK((_gMIO_PM_MapBase + REG_PM_BASE) + … macro
1327 HAL_PM_WriteRegBit(REG_PM_PWM0_IS_GPIO, BITS(5:5, 0), BMASK(5:5)); in HAL_PM_PWM_Enable()
1328 HAL_PM_WriteRegBit(reg_pwm_as_chip_config, BITS(0:0, 0), BMASK(0:0));//reg_pwm_pm_is_PWM in HAL_PM_PWM_Enable()
1354 HAL_PM_WriteRegBit(REG_PM_PWM0_PORARITY, BITS(0:0, bPolPWM), BMASK(0:0)); in HAL_PM_PWM_Polarity()
1359 HAL_PM_WriteRegBit(REG_PM_PWM0_DBEN, BITS(1:1, bdbenPWM), BMASK(1:1)); in HAL_PM_PWM_DBen()
1371 HAL_PM_WriteRegBit(REG_INV_3D_FLAG,BITS(15:15,bInvPWM),BMASK(15:15)); in HAL_PWM_INV_3D_Flag()
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| /utopia/UTPA2-700.0.x/modules/pwm/hal/macan/pwm/ |
| H A D | halPWM.c | 140 #define HAL_PM_WriteRegBit(addr, val, mask) WRITE_WORD_MASK((_gMIO_PM_MapBase + REG_PM_BASE) + ((ad… macro
1322 HAL_PM_WriteRegBit(REG_PM_PWM0_IS_GPIO,BITS(5:5,0),BMASK(5:5)); in HAL_PM_PWM_Enable()
1323 HAL_PM_WriteRegBit(reg_pwm_as_chip_config,BITS(0:0,0),BMASK(0:0));//reg_pwm_pm_is_PWM in HAL_PM_PWM_Enable()
1349 HAL_PM_WriteRegBit(REG_PM_PWM0_PORARITY,BITS(0:0,bPolPWM),BMASK(0:0)); in HAL_PM_PWM_Polarity()
1354 HAL_PM_WriteRegBit(REG_PM_PWM0_DBEN,BITS(1:1,bdbenPWM),BMASK(1:1)); in HAL_PM_PWM_DBen()
1366 HAL_PM_WriteRegBit(REG_INV_3D_FLAG,BITS(15:15,bInvPWM),BMASK(15:15)); in HAL_PWM_INV_3D_Flag()
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| /utopia/UTPA2-700.0.x/modules/pwm/hal/M7621/pwm/ |
| H A D | halPWM.c | 140 #define HAL_PM_WriteRegBit(addr, val, mask) WRITE_WORD_MASK((_gMIO_PM_MapBase + REG_PM_BASE) + ((ad… macro
1639 HAL_PM_WriteRegBit(REG_PM_PWM0_IS_GPIO,BITS(5:5,0),BMASK(5:5)); in HAL_PM_PWM_Enable()
1640 HAL_PM_WriteRegBit(reg_pwm_as_chip_config,BITS(0:0,0),BMASK(0:0));//reg_pwm_pm_is_PWM in HAL_PM_PWM_Enable()
1666 HAL_PM_WriteRegBit(REG_PM_PWM0_PORARITY,BITS(0:0,bPolPWM),BMASK(0:0)); in HAL_PM_PWM_Polarity()
1671 HAL_PM_WriteRegBit(REG_PM_PWM0_DBEN,BITS(1:1,bdbenPWM),BMASK(1:1)); in HAL_PM_PWM_DBen()
1683 HAL_PM_WriteRegBit(REG_INV_3D_FLAG,BITS(15:15,bInvPWM),BMASK(15:15)); in HAL_PWM_INV_3D_Flag()
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| /utopia/UTPA2-700.0.x/modules/pwm/hal/maserati/pwm/ |
| H A D | halPWM.c | 140 #define HAL_PM_WriteRegBit(addr, val, mask) WRITE_WORD_MASK((_gMIO_PM_MapBase + REG_PM_BASE) + ((ad… macro
1640 HAL_PM_WriteRegBit(REG_PM_PWM0_IS_GPIO,BITS(5:5,0),BMASK(5:5)); in HAL_PM_PWM_Enable()
1641 HAL_PM_WriteRegBit(reg_pwm_as_chip_config,BITS(0:0,0),BMASK(0:0));//reg_pwm_pm_is_PWM in HAL_PM_PWM_Enable()
1667 HAL_PM_WriteRegBit(REG_PM_PWM0_PORARITY,BITS(0:0,bPolPWM),BMASK(0:0)); in HAL_PM_PWM_Polarity()
1672 HAL_PM_WriteRegBit(REG_PM_PWM0_DBEN,BITS(1:1,bdbenPWM),BMASK(1:1)); in HAL_PM_PWM_DBen()
1684 HAL_PM_WriteRegBit(REG_INV_3D_FLAG,BITS(15:15,bInvPWM),BMASK(15:15)); in HAL_PWM_INV_3D_Flag()
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| /utopia/UTPA2-700.0.x/modules/pwm/hal/M7821/pwm/ |
| H A D | halPWM.c | 140 #define HAL_PM_WriteRegBit(addr, val, mask) WRITE_WORD_MASK((_gMIO_PM_MapBase + REG_PM_BASE) + ((ad… macro
1640 HAL_PM_WriteRegBit(REG_PM_PWM0_IS_GPIO,BITS(5:5,0),BMASK(5:5)); in HAL_PM_PWM_Enable()
1641 HAL_PM_WriteRegBit(reg_pwm_as_chip_config,BITS(0:0,0),BMASK(0:0));//reg_pwm_pm_is_PWM in HAL_PM_PWM_Enable()
1667 HAL_PM_WriteRegBit(REG_PM_PWM0_PORARITY,BITS(0:0,bPolPWM),BMASK(0:0)); in HAL_PM_PWM_Polarity()
1672 HAL_PM_WriteRegBit(REG_PM_PWM0_DBEN,BITS(1:1,bdbenPWM),BMASK(1:1)); in HAL_PM_PWM_DBen()
1684 HAL_PM_WriteRegBit(REG_INV_3D_FLAG,BITS(15:15,bInvPWM),BMASK(15:15)); in HAL_PWM_INV_3D_Flag()
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| /utopia/UTPA2-700.0.x/modules/pwm/hal/messi/pwm/ |
| H A D | halPWM.c | 141 #define HAL_PM_WriteRegBit(addr, val, mask) WRITE_WORD_MASK((_gMIO_PM_MapBase + REG_PM_BASE) + ((ad… macro
1647 HAL_PM_WriteRegBit(REG_PM_PWM0_IS_GPIO,BITS(5:5,0),BMASK(5:5)); in HAL_PM_PWM_Enable()
1648 HAL_PM_WriteRegBit(reg_pwm_as_chip_config,BITS(0:0,0),BMASK(0:0));//reg_pwm_pm_is_PWM in HAL_PM_PWM_Enable()
1674 HAL_PM_WriteRegBit(REG_PM_PWM0_PORARITY,BITS(0:0,bPolPWM),BMASK(0:0)); in HAL_PM_PWM_Polarity()
1679 HAL_PM_WriteRegBit(REG_PM_PWM0_DBEN,BITS(1:1,bdbenPWM),BMASK(1:1)); in HAL_PM_PWM_DBen()
1691 HAL_PM_WriteRegBit(REG_INV_3D_FLAG,BITS(15:15,bInvPWM),BMASK(15:15)); in HAL_PWM_INV_3D_Flag()
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| /utopia/UTPA2-700.0.x/modules/pwm/hal/mooney/pwm/ |
| H A D | halPWM.c | 140 #define HAL_PM_WriteRegBit(addr, val, mask) WRITE_WORD_MASK((_gMIO_PM_MapBase + REG_PM_BASE) + ((ad… macro
1639 HAL_PM_WriteRegBit(REG_PM_PWM0_IS_GPIO,BITS(5:5,0),BMASK(5:5)); in HAL_PM_PWM_Enable()
1640 HAL_PM_WriteRegBit(reg_pwm_as_chip_config,BITS(0:0,0),BMASK(0:0));//reg_pwm_pm_is_PWM in HAL_PM_PWM_Enable()
1666 HAL_PM_WriteRegBit(REG_PM_PWM0_PORARITY,BITS(0:0,bPolPWM),BMASK(0:0)); in HAL_PM_PWM_Polarity()
1671 HAL_PM_WriteRegBit(REG_PM_PWM0_DBEN,BITS(1:1,bdbenPWM),BMASK(1:1)); in HAL_PM_PWM_DBen()
1683 HAL_PM_WriteRegBit(REG_INV_3D_FLAG,BITS(15:15,bInvPWM),BMASK(15:15)); in HAL_PWM_INV_3D_Flag()
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| /utopia/UTPA2-700.0.x/modules/pwm/hal/mainz/pwm/ |
| H A D | halPWM.c | 141 #define HAL_PM_WriteRegBit(addr, val, mask) WRITE_WORD_MASK((_gMIO_PM_MapBase + REG_PM_BASE) + ((ad… macro
1642 HAL_PM_WriteRegBit(REG_PM_PWM0_IS_GPIO,BITS(5:5,0),BMASK(5:5)); in HAL_PM_PWM_Enable()
1643 HAL_PM_WriteRegBit(reg_pwm_as_chip_config,BITS(0:0,0),BMASK(0:0));//reg_pwm_pm_is_PWM in HAL_PM_PWM_Enable()
1669 HAL_PM_WriteRegBit(REG_PM_PWM0_PORARITY,BITS(0:0,bPolPWM),BMASK(0:0)); in HAL_PM_PWM_Polarity()
1674 HAL_PM_WriteRegBit(REG_PM_PWM0_DBEN,BITS(1:1,bdbenPWM),BMASK(1:1)); in HAL_PM_PWM_DBen()
1686 HAL_PM_WriteRegBit(REG_INV_3D_FLAG,BITS(15:15,bInvPWM),BMASK(15:15)); in HAL_PWM_INV_3D_Flag()
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| /utopia/UTPA2-700.0.x/modules/pwm/hal/maxim/pwm/ |
| H A D | halPWM.c | 140 #define HAL_PM_WriteRegBit(addr, val, mask) WRITE_WORD_MASK((_gMIO_PM_MapBase + REG_PM_BASE) + ((ad… macro
1639 HAL_PM_WriteRegBit(REG_PM_PWM0_IS_GPIO,BITS(5:5,0),BMASK(5:5)); in HAL_PM_PWM_Enable()
1640 HAL_PM_WriteRegBit(reg_pwm_as_chip_config,BITS(0:0,0),BMASK(0:0));//reg_pwm_pm_is_PWM in HAL_PM_PWM_Enable()
1666 HAL_PM_WriteRegBit(REG_PM_PWM0_PORARITY,BITS(0:0,bPolPWM),BMASK(0:0)); in HAL_PM_PWM_Polarity()
1671 HAL_PM_WriteRegBit(REG_PM_PWM0_DBEN,BITS(1:1,bdbenPWM),BMASK(1:1)); in HAL_PM_PWM_DBen()
1683 HAL_PM_WriteRegBit(REG_INV_3D_FLAG,BITS(15:15,bInvPWM),BMASK(15:15)); in HAL_PWM_INV_3D_Flag()
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