| /utopia/UTPA2-700.0.x/modules/dmx/hal/kano/fq/ |
| H A D | halFQ.c | 99 #define FQ32_W(reg, value); { (reg)->L = ((value) & 0x0000FFFF); \ macro
154 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_head), MIU_FQ(phyMiuOffsetFQBuf) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
155 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_tail), MIU_FQ(u32EndAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
156 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_mid), MIU_FQ(phyMiuOffsetFQBuf) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
161 FQ32_W(&(_REGFIQ[u32FQEng].rush_addr), MIU_FQ(u32RushAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetRushAddr()
296 FQ32_W(&(_REGFIQ[u32FQEng].lpcr1), u32Stamp); in HAL_FQ_SetPVRTimeStamp()
|
| /utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/fq/ |
| H A D | halFQ.c | 99 #define FQ32_W(reg, value); { (reg)->L = ((value) & 0x0000FFFF); \ macro
153 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_head), MIU_FQ(phyMiuOffsetFQBuf) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
154 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_tail), MIU_FQ(u32EndAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
155 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_mid), MIU_FQ(phyMiuOffsetFQBuf) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
160 FQ32_W(&(_REGFIQ[u32FQEng].rush_addr), MIU_FQ(u32RushAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetRushAddr()
295 FQ32_W(&(_REGFIQ[u32FQEng].lpcr1), u32Stamp); in HAL_FQ_SetPVRTimeStamp()
|
| /utopia/UTPA2-700.0.x/modules/dmx/hal/k6/fq/ |
| H A D | halFQ.c | 99 #define FQ32_W(reg, value); { (reg)->L = ((value) & 0x0000FFFF); \ macro
153 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_head), MIU_FQ(phyMiuOffsetFQBuf) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
154 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_tail), MIU_FQ(u32EndAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
155 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_mid), MIU_FQ(phyMiuOffsetFQBuf) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
160 FQ32_W(&(_REGFIQ[u32FQEng].rush_addr), MIU_FQ(u32RushAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetRushAddr()
295 FQ32_W(&(_REGFIQ[u32FQEng].lpcr1), u32Stamp); in HAL_FQ_SetPVRTimeStamp()
|
| /utopia/UTPA2-700.0.x/modules/dmx/hal/curry/fq/ |
| H A D | halFQ.c | 105 #define FQ32_W(reg, value); { (reg)->L = ((value) & 0x0000FFFF); \ macro
176 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_head), MIU_FQ(u32StartAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
177 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_tail), MIU_FQ(u32EndAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
178 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_mid), MIU_FQ(u32StartAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
183 FQ32_W(&(_REGFIQ[u32FQEng].rush_addr), MIU_FQ(u32RushAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetRushAddr()
318 FQ32_W(&(_REGFIQ[u32FQEng].lpcr1), u32Stamp); in HAL_FQ_SetPVRTimeStamp()
|
| /utopia/UTPA2-700.0.x/modules/dmx/hal/macan/fq/ |
| H A D | halFQ.c | 104 #define FQ32_W(reg, value); { (reg)->L = ((value) & 0x0000FFFF); \ macro
164 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_head), MIU_FQ(u32StartAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
165 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_tail), MIU_FQ(u32EndAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
166 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_mid), MIU_FQ(u32StartAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
171 FQ32_W(&(_REGFIQ[u32FQEng].rush_addr), MIU_FQ(u32RushAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetRushAddr()
|
| /utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/fq/ |
| H A D | halFQ.c | 99 #define FQ32_W(reg, value); { (reg)->L = ((value) & 0x0000FFFF); \ macro
153 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_head), MIU_FQ(phyMiuOffsetFQBuf) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
154 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_tail), MIU_FQ(u32EndAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
155 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_mid), MIU_FQ(phyMiuOffsetFQBuf) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
160 FQ32_W(&(_REGFIQ[u32FQEng].rush_addr), MIU_FQ(u32RushAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetRushAddr()
335 FQ32_W(&(_REGFIQ[u32FQEng].lpcr1), u32Stamp); in HAL_FQ_SetPVRTimeStamp()
|
| /utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/fq/ |
| H A D | halFQ.c | 104 #define FQ32_W(reg, value); { (reg)->L = ((value) & 0x0000FFFF); \ macro
167 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_head), MIU_FQ(u32StartAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
168 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_tail), MIU_FQ(u32EndAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
169 FQ32_W(&(_REGFIQ[u32FQEng].str2mi_mid), MIU_FQ(u32StartAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetBuf()
174 FQ32_W(&(_REGFIQ[u32FQEng].rush_addr), MIU_FQ(u32RushAddr) & FIQ_STR2MI2_ADDR_MASK); in HAL_FQ_PVR_SetRushAddr()
|
| /utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/fq/ |
| H A D | halFQ.c | 111 #define FQ32_W(reg, value); { (reg)->L = ((value) & 0x0000FFFF); \ macro
194 …FQ32_W(&(_REGFIQ[u32FQEng].str2mi_head), MIU_FQ((MS_U32)(phyStartAddr-_phyFQMiuOffset[u32FQEng])) … in HAL_FQ_PVR_SetBuf()
195 …FQ32_W(&(_REGFIQ[u32FQEng].str2mi_tail), MIU_FQ((MS_U32)(phyEndAddr-_phyFQMiuOffset[u32FQEng])) & … in HAL_FQ_PVR_SetBuf()
196 …FQ32_W(&(_REGFIQ[u32FQEng].str2mi_mid), MIU_FQ((MS_U32)(phyStartAddr-_phyFQMiuOffset[u32FQEng])) &… in HAL_FQ_PVR_SetBuf()
202 …FQ32_W(&(_REGFIQ[u32FQEng].rush_addr), MIU_FQ((MS_U32)(phyRushAddr-_phyFQMiuOffset[u32FQEng])) & F… in HAL_FQ_PVR_SetRushAddr()
|
| /utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/fq/ |
| H A D | halFQ.c | 111 #define FQ32_W(reg, value); { (reg)->L = ((value) & 0x0000FFFF); \ macro
194 …FQ32_W(&(_REGFIQ[u32FQEng].str2mi_head), MIU_FQ((MS_U32)(phyStartAddr-_phyFQMiuOffset[u32FQEng])) … in HAL_FQ_PVR_SetBuf()
195 …FQ32_W(&(_REGFIQ[u32FQEng].str2mi_tail), MIU_FQ((MS_U32)(phyEndAddr-_phyFQMiuOffset[u32FQEng])) & … in HAL_FQ_PVR_SetBuf()
196 …FQ32_W(&(_REGFIQ[u32FQEng].str2mi_mid), MIU_FQ((MS_U32)(phyStartAddr-_phyFQMiuOffset[u32FQEng])) &… in HAL_FQ_PVR_SetBuf()
202 …FQ32_W(&(_REGFIQ[u32FQEng].rush_addr), MIU_FQ((MS_U32)(phyRushAddr-_phyFQMiuOffset[u32FQEng])) & F… in HAL_FQ_PVR_SetRushAddr()
|
| /utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/fq/ |
| H A D | halFQ.c | 111 #define FQ32_W(reg, value); { (reg)->L = ((value) & 0x0000FFFF); \ macro
195 …FQ32_W(&(_REGFIQ[u32FQEng].str2mi_head), MIU_FQ((MS_U32)(phyStartAddr-_phyFQMiuOffset[u32FQEng])) … in HAL_FQ_PVR_SetBuf()
196 …FQ32_W(&(_REGFIQ[u32FQEng].str2mi_tail), MIU_FQ((MS_U32)(phyEndAddr-_phyFQMiuOffset[u32FQEng])) & … in HAL_FQ_PVR_SetBuf()
197 …FQ32_W(&(_REGFIQ[u32FQEng].str2mi_mid), MIU_FQ((MS_U32)(phyStartAddr-_phyFQMiuOffset[u32FQEng])) &… in HAL_FQ_PVR_SetBuf()
203 …FQ32_W(&(_REGFIQ[u32FQEng].rush_addr), MIU_FQ((MS_U32)(phyRushAddr-_phyFQMiuOffset[u32FQEng])) & F… in HAL_FQ_PVR_SetRushAddr()
|
| /utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/fq/ |
| H A D | halFQ.c | 111 #define FQ32_W(reg, value); { (reg)->L = ((value) & 0x0000FFFF); \ macro
195 …FQ32_W(&(_REGFIQ[u32FQEng].str2mi_head), MIU_FQ((MS_U32)(phyStartAddr-_phyFQMiuOffset[u32FQEng])) … in HAL_FQ_PVR_SetBuf()
196 …FQ32_W(&(_REGFIQ[u32FQEng].str2mi_tail), MIU_FQ((MS_U32)(phyEndAddr-_phyFQMiuOffset[u32FQEng])) & … in HAL_FQ_PVR_SetBuf()
197 …FQ32_W(&(_REGFIQ[u32FQEng].str2mi_mid), MIU_FQ((MS_U32)(phyStartAddr-_phyFQMiuOffset[u32FQEng])) &… in HAL_FQ_PVR_SetBuf()
203 …FQ32_W(&(_REGFIQ[u32FQEng].rush_addr), MIU_FQ((MS_U32)(phyRushAddr-_phyFQMiuOffset[u32FQEng])) & F… in HAL_FQ_PVR_SetRushAddr()
|