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Searched refs:ENABLE (Results 1 – 25 of 423) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vd/hal/M7821/avd/
H A DhalAVD.c6328 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_SetClock()
6392 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_SetClock()
6514 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_LoadDSP()
6523 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6562 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6606 HAL_AVD_AFEC_SetClock(ENABLE); in HAL_AVD_RegInit()
6607 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6621 RIU_WriteRegBit(BK_AFEC_DB, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6827 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
6839 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_AFEC_McuReset()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/kano/avd/
H A DhalAVD.c6328 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_SetClock()
6392 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_SetClock()
6514 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_LoadDSP()
6523 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6562 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6606 HAL_AVD_AFEC_SetClock(ENABLE); in HAL_AVD_RegInit()
6607 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6621 RIU_WriteRegBit(BK_AFEC_DB, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6827 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
6839 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_AFEC_McuReset()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/manhattan/avd/
H A DhalAVD.c6327 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_SetClock()
6391 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_SetClock()
6513 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_LoadDSP()
6522 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6561 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6605 HAL_AVD_AFEC_SetClock(ENABLE); in HAL_AVD_RegInit()
6606 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6620 RIU_WriteRegBit(BK_AFEC_DB, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6826 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
6838 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_AFEC_McuReset()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/M7621/avd/
H A DhalAVD.c6328 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_SetClock()
6392 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_SetClock()
6514 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_LoadDSP()
6523 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6562 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6606 HAL_AVD_AFEC_SetClock(ENABLE); in HAL_AVD_RegInit()
6607 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6621 RIU_WriteRegBit(BK_AFEC_DB, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6827 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
6839 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_AFEC_McuReset()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/maserati/avd/
H A DhalAVD.c6328 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_SetClock()
6392 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_SetClock()
6514 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_LoadDSP()
6523 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6562 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6606 HAL_AVD_AFEC_SetClock(ENABLE); in HAL_AVD_RegInit()
6607 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6621 RIU_WriteRegBit(BK_AFEC_DB, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6827 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
6839 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_AFEC_McuReset()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/maxim/avd/
H A DhalAVD.c6328 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_SetClock()
6392 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_SetClock()
6514 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_LoadDSP()
6523 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6562 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6606 HAL_AVD_AFEC_SetClock(ENABLE); in HAL_AVD_RegInit()
6607 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6621 RIU_WriteRegBit(BK_AFEC_DB, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6827 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
6839 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_AFEC_McuReset()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/macan/avd/
H A DhalAVD.c6315 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_SetClock()
6373 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_SetClock()
6495 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_LoadDSP()
6504 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6543 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6583 HAL_AVD_AFEC_SetClock(ENABLE); in HAL_AVD_RegInit()
6584 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6598 RIU_WriteRegBit(BK_AFEC_DB, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6804 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
6809 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_AFEC_McuReset()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/mainz/avd/
H A DhalAVD.c2969 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_SetClock()
3027 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_SetClock()
3126 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_LoadDSP()
3135 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3174 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3214 HAL_AVD_AFEC_SetClock(ENABLE); in HAL_AVD_RegInit()
3215 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
3432 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
3437 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_AFEC_McuReset()
3473 RIU_WriteRegBit(VD_MCU_RST, ENABLE, BIT(0)); //halt VD MCU first in HAL_AVD_AFEC_SetClock()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/mustang/avd/
H A DhalAVD.c6313 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_SetClock()
6371 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_SetClock()
6493 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_LoadDSP()
6502 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6541 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6580 HAL_AVD_AFEC_SetClock(ENABLE); in HAL_AVD_RegInit()
6581 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6788 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
6793 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_AFEC_McuReset()
6829 RIU_WriteRegBit(VD_MCU_RST, ENABLE, BIT(0)); //halt VD MCU first in HAL_AVD_AFEC_SetClock()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/maldives/avd/
H A DhalAVD.c6313 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_SetClock()
6371 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_SetClock()
6493 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_LoadDSP()
6502 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6541 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
6580 HAL_AVD_AFEC_SetClock(ENABLE); in HAL_AVD_RegInit()
6581 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
6788 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
6793 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_AFEC_McuReset()
6829 RIU_WriteRegBit(VD_MCU_RST, ENABLE, BIT(0)); //halt VD MCU first in HAL_AVD_AFEC_SetClock()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/messi/avd/
H A DhalAVD.c2969 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_SetClock()
3027 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_SetClock()
3126 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_LoadDSP()
3135 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3174 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3214 HAL_AVD_AFEC_SetClock(ENABLE); in HAL_AVD_RegInit()
3215 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
3432 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
3437 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_AFEC_McuReset()
3473 RIU_WriteRegBit(VD_MCU_RST, ENABLE, BIT(0)); //halt VD MCU first in HAL_AVD_AFEC_SetClock()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/mooney/avd/
H A DhalAVD.c2968 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_SetClock()
3026 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_SetClock()
3125 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_VDMCU_LoadDSP()
3134 RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3173 RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0)); in HAL_AVD_VDMCU_LoadDSP()
3213 HAL_AVD_AFEC_SetClock(ENABLE); in HAL_AVD_RegInit()
3214 RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7)); in HAL_AVD_RegInit()
3431 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
3436 HAL_AVD_VDMCU_SetFreeze(ENABLE); in HAL_AVD_AFEC_McuReset()
3472 RIU_WriteRegBit(VD_MCU_RST, ENABLE, BIT(0)); //halt VD MCU first in HAL_AVD_AFEC_SetClock()
[all …]
/utopia/UTPA2-700.0.x/modules/ve/drv/ve/
H A DdrvTVEncoder.c1039 Hal_VE_set_sog(ENABLE); // enable sog in _MDrv_VE_SetInputSource()
1051 Hal_VE_set_rgb_in(ENABLE); // enable RGB in in _MDrv_VE_SetInputSource()
1056 Hal_VE_set_ccir656_in(ENABLE); in _MDrv_VE_SetInputSource()
1236 Hal_VE_set_clk_on_off(ENABLE); in _MDrv_VE_SetOutputCtrl()
1240 Hal_VE_set_vbi(ENABLE); in _MDrv_VE_SetOutputCtrl()
1244 Hal_VE_sofeware_reset(ENABLE); // software reset in _MDrv_VE_SetOutputCtrl()
1245 Hal_VE_set_reg_load(ENABLE);// load register,but not affect bit3(VBI output) in _MDrv_VE_SetOutputCtrl()
1263 Hal_VE_set_ve_on_off(ENABLE); in _MDrv_VE_SetOutputCtrl()
1619 if(g_VEInfo.stVECusScalingInfo.bHCusScalingEnable==ENABLE) in MDrv_VE_set_scaling_ratio()
1639 if(g_VEInfo.stVECusScalingInfo.bVCusScalingEnable==ENABLE) in MDrv_VE_set_scaling_ratio()
[all …]
/utopia/UTPA2-700.0.x/modules/bdma/hal/mustang/bdma/
H A DhalBDMA.h116 #define BDMA_MEM_FILL (ENABLE)
117 #define BDMA_FLASH_COPY (ENABLE)
118 #define BDMA_DUMMY_WRCNT (ENABLE)
119 #define BDMA_DEV_DATA_WIDTH (ENABLE) //device data width
120 #define BDMA_DMDMCU (ENABLE)
121 #define BDMA_TSP (ENABLE)
122 #define BDMA_DSP (ENABLE)
123 #define BDMA_HK51_1KSRAM (ENABLE)
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/
H A Dmdrv_sc_DIPscaling.c266 MDrv_XC_DWIN_DisableInputSource(pInstance,ENABLE, eWindow); in MDrv_XC_DIP_Init()
270 MDrv_XC_DWIN_Disable_IPM_ReadWriteRequest(pInstance,ENABLE, eWindow); in MDrv_XC_DIP_Init()
272 MDrv_XC_DWIN_EnableIPAutoCoast(pInstance,ENABLE, eWindow); in MDrv_XC_DIP_Init()
420 Hal_SC_DWIN_set_image_wrap( pInstance, ENABLE, ENABLE, eWindow ); in MDrv_XC_DWIN_SetInputSource()
430 Hal_SC_DWIN_set_input_10bit( pInstance, ENABLE, eWindow ); in MDrv_XC_DWIN_SetInputSource()
433 Hal_SC_DWIN_set_ms_filter(pInstance, ENABLE, 0, eWindow); in MDrv_XC_DWIN_SetInputSource()
442 Hal_SC_DWIN_set_ms_filter(pInstance, ENABLE, 0, eWindow); in MDrv_XC_DWIN_SetInputSource()
444 Hal_SC_DWIN_set_input_10bit( pInstance, ENABLE, eWindow ); in MDrv_XC_DWIN_SetInputSource()
449 Hal_SC_DWIN_set_post_glitch_removal( pInstance, ENABLE, 0x01, eWindow ); in MDrv_XC_DWIN_SetInputSource()
459 Hal_SC_DWIN_set_de_only_mode( pInstance, ENABLE, eWindow ); in MDrv_XC_DWIN_SetInputSource()
[all …]
/utopia/UTPA2-700.0.x/modules/bdma/hal/curry/bdma/
H A DhalBDMA.h116 #define BDMA_MEM_FILL (ENABLE)
117 #define BDMA_FLASH_COPY (ENABLE)
118 #define BDMA_DUMMY_WRCNT (ENABLE)
119 #define BDMA_DEV_DATA_WIDTH (ENABLE) //device data width
120 #define BDMA_DMDMCU (ENABLE)
121 #define BDMA_TSP (ENABLE)
122 #define BDMA_DSP (ENABLE)
/utopia/UTPA2-700.0.x/modules/bdma/hal/kano/bdma/
H A DhalBDMA.h116 #define BDMA_MEM_FILL (ENABLE)
117 #define BDMA_FLASH_COPY (ENABLE)
118 #define BDMA_DUMMY_WRCNT (ENABLE)
119 #define BDMA_DEV_DATA_WIDTH (ENABLE) //device data width
120 #define BDMA_DMDMCU (ENABLE)
121 #define BDMA_TSP (ENABLE)
122 #define BDMA_DSP (ENABLE)
/utopia/UTPA2-700.0.x/modules/bdma/hal/k6/bdma/
H A DhalBDMA.h116 #define BDMA_MEM_FILL (ENABLE)
117 #define BDMA_FLASH_COPY (ENABLE)
118 #define BDMA_DUMMY_WRCNT (ENABLE)
119 #define BDMA_DEV_DATA_WIDTH (ENABLE) //device data width
120 #define BDMA_DMDMCU (ENABLE)
121 #define BDMA_TSP (ENABLE)
122 #define BDMA_DSP (ENABLE)
/utopia/UTPA2-700.0.x/modules/bdma/hal/k6lite/bdma/
H A DhalBDMA.h116 #define BDMA_MEM_FILL (ENABLE)
117 #define BDMA_FLASH_COPY (ENABLE)
118 #define BDMA_DUMMY_WRCNT (ENABLE)
119 #define BDMA_DEV_DATA_WIDTH (ENABLE) //device data width
120 #define BDMA_DMDMCU (ENABLE)
121 #define BDMA_TSP (ENABLE)
122 #define BDMA_DSP (ENABLE)
/utopia/UTPA2-700.0.x/modules/bdma/hal/manhattan/bdma/
H A DhalBDMA.h116 #define BDMA_MEM_FILL (ENABLE)
117 #define BDMA_FLASH_COPY (ENABLE)
118 #define BDMA_DUMMY_WRCNT (ENABLE)
119 #define BDMA_DEV_DATA_WIDTH (ENABLE) //device data width
120 #define BDMA_DMDMCU (ENABLE)
121 #define BDMA_TSP (ENABLE)
122 #define BDMA_DSP (ENABLE)
/utopia/UTPA2-700.0.x/modules/bdma/hal/macan/bdma/
H A DhalBDMA.h116 #define BDMA_MEM_FILL (ENABLE)
117 #define BDMA_FLASH_COPY (ENABLE)
118 #define BDMA_DUMMY_WRCNT (ENABLE)
119 #define BDMA_DEV_DATA_WIDTH (ENABLE) //device data width
120 #define BDMA_DMDMCU (ENABLE)
122 #define BDMA_DSP (ENABLE)
123 #define BDMA_HK51_1KSRAM (ENABLE)
/utopia/UTPA2-700.0.x/modules/bdma/hal/maldives/bdma/
H A DhalBDMA.h116 #define BDMA_MEM_FILL (ENABLE)
117 #define BDMA_FLASH_COPY (ENABLE)
118 #define BDMA_DUMMY_WRCNT (ENABLE)
119 #define BDMA_DEV_DATA_WIDTH (ENABLE) //device data width
120 #define BDMA_DMDMCU (ENABLE)
121 #define BDMA_TSP (ENABLE)
122 #define BDMA_DSP (ENABLE)
/utopia/UTPA2-700.0.x/modules/bdma/hal/maserati/bdma/
H A DhalBDMA.h116 #define BDMA_MEM_FILL (ENABLE)
117 #define BDMA_FLASH_COPY (ENABLE)
118 #define BDMA_DUMMY_WRCNT (ENABLE)
119 #define BDMA_DEV_DATA_WIDTH (ENABLE) //device data width
120 #define BDMA_DMDMCU (ENABLE)
122 #define BDMA_DSP (ENABLE)
123 #define BDMA_HK51_1KSRAM (ENABLE)
/utopia/UTPA2-700.0.x/modules/bdma/hal/messi/bdma/
H A DhalBDMA.h116 #define BDMA_MEM_FILL (ENABLE)
117 #define BDMA_FLASH_COPY (ENABLE)
118 #define BDMA_DUMMY_WRCNT (ENABLE)
119 #define BDMA_DEV_DATA_WIDTH (ENABLE) //device data width
120 #define BDMA_DMDMCU (ENABLE)
122 #define BDMA_DSP (ENABLE)
123 #define BDMA_HK51_1KSRAM (ENABLE)
/utopia/UTPA2-700.0.x/modules/bdma/hal/M7621/bdma/
H A DhalBDMA.h116 #define BDMA_MEM_FILL (ENABLE)
117 #define BDMA_FLASH_COPY (ENABLE)
118 #define BDMA_DUMMY_WRCNT (ENABLE)
119 #define BDMA_DEV_DATA_WIDTH (ENABLE) //device data width
120 #define BDMA_DMDMCU (ENABLE)
122 #define BDMA_DSP (ENABLE)
123 #define BDMA_HK51_1KSRAM (ENABLE)

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