2969     HAL_AVD_VDMCU_SetFreeze(ENABLE);  in HAL_AVD_VDMCU_SetClock()
3027     HAL_AVD_VDMCU_SetFreeze(ENABLE);  in HAL_AVD_VDMCU_SetClock()
3126     HAL_AVD_VDMCU_SetFreeze(ENABLE);  in HAL_AVD_VDMCU_LoadDSP()
3135     RIU_WriteRegBit(VD_MCU_ADDR_AUTO_INC, ENABLE, BIT(0));  in HAL_AVD_VDMCU_LoadDSP()
3174     RIU_WriteRegBit(VD_MCU_SRAM_EN, ENABLE, BIT(0));  in HAL_AVD_VDMCU_LoadDSP()
3214     HAL_AVD_AFEC_SetClock(ENABLE);  in HAL_AVD_RegInit()
3215     RIU_WriteRegBit(BK_AFEC_14, ENABLE, BIT(7));  in HAL_AVD_RegInit()
3432     RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7));  in HAL_AVD_AFEC_McuReset()
3437     HAL_AVD_VDMCU_SetFreeze(ENABLE);  in HAL_AVD_AFEC_McuReset()
3473         RIU_WriteRegBit(VD_MCU_RST, ENABLE, BIT(0));   //halt VD MCU first  in HAL_AVD_AFEC_SetClock()
3509 …RIU_WriteRegBit(L_BK_ADC_ATOP(0x00), ENABLE, BIT(3)); //enable adc clock, TODO check with analog R…  in HAL_AVD_AFEC_SetClockSource()
3510         RIU_WriteRegBit(L_BK_ADC_ATOP(0x03), ENABLE, BIT(1)); //use ADCPLB  in HAL_AVD_AFEC_SetClockSource()
3530         RIU_WriteRegBit(L_BK_CLKGEN0(0x00), ENABLE, BIT(4));  in HAL_AVD_AFEC_SetClockSource()
3590         RIU_WriteRegBit(BK_AFEC_CE, ENABLE, BIT(5));  in HAL_AVD_AFEC_SetPatchFlag()
3620     HAL_AVD_AFEC_SetClock(ENABLE);  in HAL_AVD_AFEC_SetInput()
3643         RIU_WriteRegBit (L_BK_ADC_ATOP(0x40), ENABLE, BIT(6)); // i.e. 0x80[6]  in HAL_AVD_AFEC_SetInput()
3699             RIU_WriteRegBit (BK_COMB_10, ENABLE, BIT(7)); // <- SET COMB  in HAL_AVD_AFEC_SetInput()
3704             RIU_WriteRegBit( BK_AFEC_1F, ENABLE, BIT(7)); // Enable clamp C  in HAL_AVD_AFEC_SetInput()
3737 … RIU_WriteRegBit (H_BK_ADC_ATOP(0x2D), ENABLE, BIT(6)); // i.e. ATOP 0x5C disable ADC clamp from VD  in HAL_AVD_AFEC_SetInput()
3753         HAL_AVD_AFEC_EnableCVBSLPF(ENABLE);  in HAL_AVD_AFEC_SetInput()
3757             RIU_WriteRegBit(BK_AFEC_8F,ENABLE,BIT(5));  in HAL_AVD_AFEC_SetInput()
3766             RIU_WriteRegBit(BK_AFEC_CF,ENABLE,BIT(7));  in HAL_AVD_AFEC_SetInput()
3767             RIU_WriteRegBit(H_BK_CHIPTOP(0x13), ENABLE, BIT(8));  //20090611EL  in HAL_AVD_AFEC_SetInput()
3768 …RIU_WriteRegBit(BK_AFEC_40,ENABLE,BIT(4)); // BY 20090630 put gain setting temporarily, TODO move …  in HAL_AVD_AFEC_SetInput()
3769             RIU_WriteRegBit(BK_AFEC_40,ENABLE,BIT(7)); // enable VIF in hardware  in HAL_AVD_AFEC_SetInput()
3882     RIU_WriteRegBit(BK_AFEC_A0, ENABLE, (BIT(7)));  in HAL_AVD_AFEC_SetHTotal()
3995         HAL_AVD_AFEC_Set656DCOffset(ENABLE);  in HAL_AVD_AFEC_SetFSCMode()
4085     RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2));  in HAL_AVD_AFEC_AGCSetMode()
4106     RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2));  in HAL_AVD_AFEC_AGCSetCoarseGain()
4127     RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2));  in HAL_AVD_AFEC_AGCSetFineGain()
4273 …RIU_WriteRegBit(BK_COMB_4C, ENABLE, BIT(7));                    // BK_COMB_4C[7] COMB memory prote…  in HAL_AVD_COMB_SetMemoryProtect()
4293         RIU_WriteRegBit(BK_COMB_EE, ENABLE, BIT(7));  in HAL_AVD_COMB_Set3dCombMid()
4294         RIU_WriteRegBit(BK_COMB_2D, ENABLE, BIT(4));  in HAL_AVD_COMB_Set3dCombMid()
4320 …  RIU_WriteRegBit( BK_COMB_2D, ENABLE, BIT(4));   // T3 Transition Vertical line in channel change.  in HAL_AVD_COMB_Set3dComb()
4572         RIU_WriteRegBit(BK_COMB_18, ENABLE, BIT(0));  in HAL_AVD_COMB_SetNonStandardHtotal()
4579         RIU_WriteRegBit(BK_COMB_C0, ENABLE, BIT(5));  in HAL_AVD_COMB_SetNonStandardHtotal()
4654         RIU_WriteRegBit(BK_VBI_8D, ENABLE, BIT(6));  in HAL_AVD_VBI_SetTTSigDetSel()
4727     RIU_WriteRegBit(BK_AFEC_55, ENABLE, BIT(2));  in HAL_AVD_SetPQFineTune()