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Searched refs:DDR_FREQ_INPUT_DIV_2 (Results 1 – 7 of 7) sorted by relevance

/utopia/UTPA2-700.0.x/modules/miu/hal/maldives/miu/
H A DregMIU.h130 #define DDR_FREQ_INPUT_DIV_2 (MIU_REG_BASE+0x26) //0x1226 macro
/utopia/UTPA2-700.0.x/modules/miu/hal/manhattan/miu/
H A DregMIU.h135 #define DDR_FREQ_INPUT_DIV_2 (MIU_REG_BASE+0x26) //0x1226 macro
/utopia/UTPA2-700.0.x/modules/miu/hal/curry/miu/
H A DregMIU.h130 #define DDR_FREQ_INPUT_DIV_2 (MIU_REG_BASE+0x26) //0x1226 macro
/utopia/UTPA2-700.0.x/modules/miu/hal/kano/miu/
H A DregMIU.h130 #define DDR_FREQ_INPUT_DIV_2 (MIU_REG_BASE+0x26) //0x1226 macro
/utopia/UTPA2-700.0.x/modules/miu/hal/M7821/miu/
H A DregMIU.h138 #define DDR_FREQ_INPUT_DIV_2 (MIU_REG_BASE+0x26) //0x1226 macro
/utopia/UTPA2-700.0.x/modules/miu/hal/maserati/miu/
H A DregMIU.h138 #define DDR_FREQ_INPUT_DIV_2 (MIU_REG_BASE+0x26) //0x1226 macro
/utopia/UTPA2-700.0.x/modules/miu/hal/macan/miu/
H A DregMIU.h135 #define DDR_FREQ_INPUT_DIV_2 (MIU_REG_BASE+0x26) //0x1226 macro