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Searched refs:CKG_IDCLK3_MASK (Results 1 – 25 of 38) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dmhal_xc_chip_config.h592 #define CKG_IDCLK3_MASK BMASK(8:6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dmhal_xc_chip_config.h592 #define CKG_IDCLK3_MASK BMASK(8:6) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_mux.c463 MDrv_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux << 2, CKG_IDCLK3_MASK); in Hal_SC_mux_set_dipwin_ip_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_mux.c463 MDrv_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux << 2, CKG_IDCLK3_MASK); in Hal_SC_mux_set_dipwin_ip_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_mux.c463 MDrv_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux << 2, CKG_IDCLK3_MASK); in Hal_SC_mux_set_dipwin_ip_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_mux.c463 MDrv_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux << 2, CKG_IDCLK3_MASK); in Hal_SC_mux_set_dipwin_ip_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_mux.c540 MDrv_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux << 2, CKG_IDCLK3_MASK); in Hal_SC_mux_set_dipwin_ip_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dmhal_xc_chip_config.h791 #define CKG_IDCLK3_MASK BMASK(5:2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dmhal_xc_chip_config.h797 #define CKG_IDCLK3_MASK BMASK(5:2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dmhal_xc_chip_config.h790 #define CKG_IDCLK3_MASK BMASK(5:2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dmhal_xc_chip_config.h784 #define CKG_IDCLK3_MASK BMASK(5:2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_xc_chip_config.h741 #define CKG_IDCLK3_MASK BMASK(5:2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_xc_chip_config.h845 #define CKG_IDCLK3_MASK BMASK(5:2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_mux.c592 MDrv_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux << 2, CKG_IDCLK3_MASK); in Hal_SC_mux_set_dipwin_ip_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_xc_chip_config.h805 #define CKG_IDCLK3_MASK BMASK(5:2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_mux.c592 MDrv_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux << 2, CKG_IDCLK3_MASK); in Hal_SC_mux_set_dipwin_ip_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_mux.c592 MDrv_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux << 2, CKG_IDCLK3_MASK); in Hal_SC_mux_set_dipwin_ip_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_xc_chip_config.h857 #define CKG_IDCLK3_MASK BMASK(5:2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_mux.c592 MDrv_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux << 2, CKG_IDCLK3_MASK); in Hal_SC_mux_set_dipwin_ip_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_mux.c592 MDrv_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux << 2, CKG_IDCLK3_MASK); in Hal_SC_mux_set_dipwin_ip_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_xc_chip_config.h795 #define CKG_IDCLK3_MASK BMASK(5:2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_xc_chip_config.h862 #define CKG_IDCLK3_MASK BMASK(5:2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_xc_chip_config.h849 #define CKG_IDCLK3_MASK BMASK(5:2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_mux.c592 MDrv_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux << 2, CKG_IDCLK3_MASK); in Hal_SC_mux_set_dipwin_ip_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_dip.c1003 W2BYTEMSK( REG_CKG_IDCLK3, u16Clk_Mux ,CKG_IDCLK3_MASK); in HAL_XC_DIP_SetMux()

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