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Searched refs:CKG_FCLK_MASK (Results 1 – 25 of 64) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_sc.c4936 MS_U8 u8FClkReg = MDrv_ReadByte(REG_CKG_FCLK) & CKG_FCLK_MASK; in _Hal_SC_get_Fclk()
4987 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4988 MDrv_WriteByteMask(REG_CKG_EDCLK, CKG_EDCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4995 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_320MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4996 MDrv_WriteByteMask(REG_CKG_EDCLK, CKG_EDCLK_320MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5000 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5001 MDrv_WriteByteMask(REG_CKG_EDCLK, CKG_EDCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5026 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5027 MDrv_WriteByteMask(REG_CKG_EDCLK, CKG_EDCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5033 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
[all …]
H A Dmhal_dip.c881 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_320MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
943 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_216MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
2873 u16tmp = MDrv_ReadByte(REG_CKG_FCLK)&CKG_FCLK_MASK; in HAL_XC_DIP_Check_Clock()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_sc.c4775 MS_U8 u8FClkReg = MDrv_ReadByte(REG_CKG_FCLK) & CKG_FCLK_MASK; in _Hal_SC_get_Fclk()
4826 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4827 MDrv_WriteByteMask(REG_CKG_EDCLK, CKG_EDCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4834 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_320MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4835 MDrv_WriteByteMask(REG_CKG_EDCLK, CKG_EDCLK_320MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4839 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4840 MDrv_WriteByteMask(REG_CKG_EDCLK, CKG_EDCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4865 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4866 MDrv_WriteByteMask(REG_CKG_EDCLK, CKG_EDCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4872 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
[all …]
H A Dmhal_dip.c879 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_320MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
941 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_216MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
2891 u16tmp = MDrv_ReadByte(REG_CKG_FCLK)&CKG_FCLK_MASK; in HAL_XC_DIP_Check_Clock()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_sc.c5086 u8FClkReg = MDrv_ReadByte(REG_CKG_FCLK) & CKG_FCLK_MASK; in _Hal_SC_get_Fclk()
5166 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5167 MDrv_WriteByteMask(REG_CKG_EDCLK, CKG_EDCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5174 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_320MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5175 MDrv_WriteByteMask(REG_CKG_EDCLK, CKG_EDCLK_320MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5179 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5180 MDrv_WriteByteMask(REG_CKG_EDCLK, CKG_EDCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5215 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5216 MDrv_WriteByteMask(REG_CKG_EDCLK, CKG_EDCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5222 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
[all …]
H A Dmhal_dip.c1382 MDrv_DIP_WriteByteMask(REG_CKG_DIP_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_Init()
1607 MDrv_DIP_WriteByteMask(REG_CKG_DIP_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
1613 MDrv_DIP_WriteByteMask(REG_CKG_DIP_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
1671 MDrv_DIP_WriteByteMask(REG_CKG_DIP_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
1679 MDrv_DIP_WriteByteMask(REG_CKG_DIP_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
4333 u16tmp = MDrv_ReadByte(REG_CKG_FCLK)&CKG_FCLK_MASK; in HAL_XC_DIP_Check_Clock()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_dip.c1529 MDrv_DIP_WriteByteMask(REG_CKG_IDCLK0, CKG_FCLK_170MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
1535 MDrv_DIP_WriteByteMask(REG_CKG_IDCLK0, CKG_FCLK_170MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
1593 MDrv_DIP_WriteByteMask(REG_CKG_IDCLK0, CKG_FCLK_170MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
1601 MDrv_DIP_WriteByteMask(REG_CKG_IDCLK0, CKG_FCLK_170MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
3861 u16tmp = MDrv_ReadByte(REG_CKG_FCLK)&CKG_FCLK_MASK; in HAL_XC_DIP_Check_Clock()
/utopia/UTPA2-700.0.x/modules/pws/hal/maldives/pws/
H A DregCLKGEN.h336 #define CKG_FCLK_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/k6/pws/
H A DregCLKGEN.h336 #define CKG_FCLK_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/macan/pws/
H A DregCLKGEN.h336 #define CKG_FCLK_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/mooney/pws/
H A DregCLKGEN.h336 #define CKG_FCLK_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/messi/pws/
H A DregCLKGEN.h336 #define CKG_FCLK_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/manhattan/pws/
H A DregCLKGEN.h336 #define CKG_FCLK_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/k6lite/pws/
H A DregCLKGEN.h336 #define CKG_FCLK_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/M7821/pws/
H A DregCLKGEN.h336 #define CKG_FCLK_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/mainz/pws/
H A DregCLKGEN.h336 #define CKG_FCLK_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/mustang/pws/
H A DregCLKGEN.h336 #define CKG_FCLK_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/maxim/pws/
H A DregCLKGEN.h336 #define CKG_FCLK_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/M7621/pws/
H A DregCLKGEN.h336 #define CKG_FCLK_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/curry/pws/
H A DregCLKGEN.h336 #define CKG_FCLK_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/kano/pws/
H A DregCLKGEN.h336 #define CKG_FCLK_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/maserati/pws/
H A DregCLKGEN.h336 #define CKG_FCLK_MASK (BIT5 | BIT4 | BIT3 | BIT2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dmhal_xc_chip_config.h512 #define CKG_FCLK_MASK BMASK(5:2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dmhal_xc_chip_config.h512 #define CKG_FCLK_MASK BMASK(5:2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dmhal_xc_chip_config.h667 #define CKG_FCLK_MASK BMASK(4:2) macro

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