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Searched refs:CKG_FCLK_345MHZ (Results 1 – 25 of 30) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_sc.c4954 else if(CKG_FCLK_345MHZ == u8FClkReg) in _Hal_SC_get_Fclk()
4987 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5000 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5026 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5033 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5045 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5053 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5077 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5107 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5127 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
[all …]
H A Dmhal_dip.c2874 if(u16tmp == CKG_FCLK_345MHZ) in HAL_XC_DIP_Check_Clock()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_sc.c4793 else if(CKG_FCLK_345MHZ == u8FClkReg) in _Hal_SC_get_Fclk()
4826 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4839 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4865 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4872 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4884 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4892 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4916 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4946 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
4966 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
[all …]
H A Dmhal_dip.c2892 if(u16tmp == CKG_FCLK_345MHZ) in HAL_XC_DIP_Check_Clock()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_xc_chip_config.h665 #define CKG_FCLK_345MHZ (2 << 2) macro
672 #define CKG_FCLK_DEFAULT CKG_FCLK_345MHZ
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_xc_chip_config.h765 #define CKG_FCLK_345MHZ (2 << 2) macro
772 #define CKG_FCLK_DEFAULT CKG_FCLK_345MHZ
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_xc_chip_config.h725 #define CKG_FCLK_345MHZ (2 << 2) macro
732 #define CKG_FCLK_DEFAULT CKG_FCLK_345MHZ
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_xc_chip_config.h777 #define CKG_FCLK_345MHZ (2 << 2) macro
784 #define CKG_FCLK_DEFAULT CKG_FCLK_345MHZ
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_xc_chip_config.h715 #define CKG_FCLK_345MHZ (2 << 2) macro
722 #define CKG_FCLK_DEFAULT CKG_FCLK_345MHZ
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_xc_chip_config.h782 #define CKG_FCLK_345MHZ (2 << 2) macro
789 #define CKG_FCLK_DEFAULT CKG_FCLK_345MHZ
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_xc_chip_config.h769 #define CKG_FCLK_345MHZ (2 << 2) macro
776 #define CKG_FCLK_DEFAULT CKG_FCLK_345MHZ
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_sc.c5104 else if(CKG_FCLK_345MHZ == u8FClkReg) in _Hal_SC_get_Fclk()
5166 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5179 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5215 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5222 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5234 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5242 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5266 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5297 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
5317 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_XC_IsForcePrescaling()
[all …]
H A Dmhal_dip.c1382 MDrv_DIP_WriteByteMask(REG_CKG_DIP_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_Init()
1607 MDrv_DIP_WriteByteMask(REG_CKG_DIP_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
1613 MDrv_DIP_WriteByteMask(REG_CKG_DIP_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
1671 MDrv_DIP_WriteByteMask(REG_CKG_DIP_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
1679 MDrv_DIP_WriteByteMask(REG_CKG_DIP_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
4334 if(u16tmp == CKG_FCLK_345MHZ) in HAL_XC_DIP_Check_Clock()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dmhal_xc_chip_config.h680 #define CKG_FCLK_345MHZ (1 << 2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dmhal_xc_chip_config.h686 #define CKG_FCLK_345MHZ (1 << 2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dmhal_xc_chip_config.h686 #define CKG_FCLK_345MHZ (1 << 2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_dip.c2531 if(u16tmp == CKG_FCLK_345MHZ) in HAL_XC_DIP_Check_Clock()
H A Dmhal_sc.c3422 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_SC_set_Fclk()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_dip.c2770 if(u16tmp == CKG_FCLK_345MHZ) in HAL_XC_DIP_Check_Clock()
H A Dmhal_sc.c3627 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in Hal_SC_set_Fclk()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_dip.c2738 if(u16tmp == CKG_FCLK_345MHZ) in HAL_XC_DIP_Check_Clock()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_dip.c3406 if(u16tmp == CKG_FCLK_345MHZ) in HAL_XC_DIP_Check_Clock()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_dip.c3354 if(u16tmp == CKG_FCLK_345MHZ) in HAL_XC_DIP_Check_Clock()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_dip.c3408 if(u16tmp == CKG_FCLK_345MHZ) in HAL_XC_DIP_Check_Clock()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_dip.c3358 if(u16tmp == CKG_FCLK_345MHZ) in HAL_XC_DIP_Check_Clock()

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